Cascade communications between FPGA tiles

Patent metadata

Field	Value
Publication number	US-11288220-B2
Application number	US-201916656685-A
Country	US
Kind code	B2
Filing date	Oct 18, 2019
Priority date	Oct 18, 2019
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.

First claim

What is claimed is:

1. A circuit comprising:
a first tile of a field programmable gate array (FPGA) comprising a first integer multiply and accumulate (MAC) circuit, a first floating-point MAC circuit, and a first memory circuit, the first integer MAC circuit coupled to a set of inputs from a connection fabric of the FPGA; and
a second tile of the FPGA comprising a second integer MAC circuit, a second floating-point MAC circuit, and a second memory circuit, the second integer MAC circuit coupled to the set of inputs from the connection fabric of the FPGA, the first memory circuit coupled to the second memory circuit by a bidirectional cascade communication channel.

2. The circuit of claim 1 , wherein:
the second floating-point MAC circuit of the FPGA is coupled to a second set of inputs from the connection fabric of the FPGA; and
the second floating-point MAC circuit of the FPGA is configured to generate a result based on a subset of the second set of inputs.

3. The circuit of claim 1 , wherein:
the second floating-point MAC circuit of the FPGA is coupled to a second set of inputs from the connection fabric of the FPGA;
in response to a first configuration signal, the second floating-point MAC circuit is configured to generate a result based on a subset of the set of inputs and the subset of the second set of inputs; and
in response to a second configuration signal, the second floating-point MAC circuit is configured to perform operations on the second set of inputs and data stored in the second memory circuit.

4. The circuit of claim 1 , wherein:
the second floating-point MAC circuit is configured to provide a result as a cascade output of the second tile of the FPGA.

5. The circuit of claim 1 , wherein:
in response to a configuration signal, the second floating-point MAC circuit is configured to receive a second set of inputs from a second cascade output of the first tile of the FPGA.

6. The circuit of claim 1 , wherein:
the second memory circuit of the second tile of the FPGA is configured to store data received from the bidirectional cascade communication channel with the first tile.

7. The circuit of claim 6 , wherein:
the second memory circuit of the second tile of the FPGA is configured to simultaneously perform a first operation and a second operation, the first operation providing first data to the second floating-point MAC circuit of the second tile of the FPGA, the second operation storing the data received from the bidirectional cascade communication channel with the first tile.

8. The circuit of claim 6 , wherein the second memory circuit is configured to provide a first set of outputs to a third tile of the FPGA via a second cascade output.

9. The circuit of claim 1 , wherein the second floating-point MAC circuit is further configured to provide a first set of outputs to a third tile of the FPGA via a second cascade output.

10. The circuit of claim 1 , wherein:
the first memory circuit of the first tile of the FPGA has a block address;
the set of inputs comprises an input block address and a mask; and
the first memory circuit of the first tile of the FPGA is configured to:
generate a modified block address based on the block address of the first memory circuit and the mask; and
store a subset of the set of inputs based on the modified block address matching the input block address.

11. A method comprising:
receiving, by a first integer multiply and accumulate (MAC) circuit of a first tile of a field programmable gate array (FPGA), a set of inputs from a connection fabric of the FPGA;
receiving, by a second integer MAC circuit of a second FPGA tile, the set of inputs from the connection fabric of the FPGA;
receiving, by a floating-point MAC circuit of the second FPGA tile, a second set of inputs from the connection fabric of the FPGA; and
communicating between a first memory circuit of the first FPGA tile and a second memory circuit of the second FPGA tile via a bidirectional cascade communication channel.

12. The method of claim 11 , further comprising:
generating, by the floating-point MAC circuit, a result based on a subset of the second set of inputs.

13. The method of claim 11 , wherein:
in response to a configuration signal, the second integer MAC circuit of the second tile of the FPGA is configured to receive, via a multiplexer, the set of inputs from a cascade output of the first tile of the FPGA.

14. The method of claim 11 , further comprising:
storing, by the second memory circuit of the second tile of the FPGA, data received from the bidirectional cascade communication channel.

15. A non-transitory machine-readable storage medium containing instructions that, when executed by one or more processors, cause the one or more processors to control configuration of a field programmable gate array (FPGA) comprising:
a first tile of the FPGA comprising a first integer multiply and accumulate (MAC) circuit, a first floating-point MAC circuit, and a first memory circuit, the first integer MAC circuit coupled to a set of inputs from a connection fabric of the FPGA; and
a second tile of the FPGA comprising a second integer MAC circuit, a second floating-point MAC circuit, and a second memory circuit, the second integer MAC circuit coupled to the set of inputs from the connection fabric of the FPGA, the first memory circuit coupled to the second memory circuit by a bidirectional cascade communication channel.

16. The non-transitory storage medium of claim 15 , wherein:
the second integer MAC circuit of the FPGA is coupled to a second set of inputs from the connection fabric of the FPGA; and
the second integer MAC circuit of the FPGA is configured to generate a result is based on a subset of the second set of inputs.

17. The non-transitory storage medium of claim 15 , wherein:
in response to a configuration signal, the second integer MAC circuit is configured to receive a second set of inputs from a second cascade output of the first tile of the FPGA.

18. The non-transitory storage medium of claim 15 , wherein:
in response to a first configuration signal, the second integer MAC circuit is configured to generate a result based on a subset of the set of inputs; and
in response to a second configuration signal, the second integer MAC circuit is configured to perform operations on data stored in the second memory circuit.

19. The non-transitory storage medium of claim 15 , wherein:
the second integer MAC circuit is configured to provide a result as a cascade output of the second tile of the FPGA.

20. The non-transitory storage medium of claim 15 , wherein:
the second memory circuit of the second tile of the FPGA is configured to store data received from the bidirectional cascade communication channel with the first tile.

Assignees

• Achronix Semiconductor Corp

Inventors

• Pugh Daniel
• Nijssen Raymond
• Fitton Michael Philip
• Van Der Goot Marcel

Classifications

• G06F13/4027 Primary

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title