Directed interrupt virtualization with running indicator

Patent metadata

Field	Value
Publication number	US-11734037-B2
Application number	US-202117482514-A
Country	US
Kind code	B2
Filing date	Sep 23, 2021
Priority date	Feb 14, 2019
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

First claim

What is claimed is:

1. A computer program product for providing an interrupt signal to a guest operating system executed using one or more processors of a plurality of processors of a computer system, the computer program product comprising:
one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media to perform a method comprising:
receiving an interrupt signal with an interrupt target ID, the interrupt target ID identifying one processor of the plurality of processors as a target processor for handling the interrupt signal;
retrieving a first copy of an interrupt table entry assigned to the interrupt target ID from an interrupt table, the first copy of the interrupt table entry comprising a first copy of a running indicator to indicate whether the target processor identified by the interrupt target ID is scheduled for usage by the guest operating system;
checking, using the first copy of the running indicator, that the target processor is scheduled for usage by the guest operating system; and
translating, based on the target processor being scheduled for usage by the guest operating system, the interrupt target ID to a logical processor ID and forwarding the interrupt signal to the target processor to handle, the forwarding using the logical processor ID resulting from the translating to address the target processor directly.

2. The computer program product of claim 1 , wherein the running indicator is implemented as a single bit.

3. The computer program product of claim 1 , wherein the interrupt signal is received in a form of a message signaled interrupt comprising the interrupt target ID of the target processor.

4. The computer program product of claim 1 , wherein the first copy of the interrupt table entry further comprises a first mapping of the interrupt target ID to the logical processor ID, and wherein the translating the interrupt target ID to the logical processor ID of the target processor comprises using the first copy of the interrupt table entry.

5. The computer program product of claim 1 , wherein the first copy of the interrupt table entry further comprises an interrupt blocking indicator to indicate whether the target processor identified by the interrupt target ID is currently blocked from receiving interrupt signals, and wherein the method further comprises:
checking, using the interrupt blocking indicator: that the target processor is blocked from receiving interrupt signals; and
blocking the interrupt signal from being forwarded to the target processor for handling, based on the target processor being blocked.

6. The computer program product of claim 5 , wherein the method further comprises forwarding the interrupt signal for handling to remaining processors of the plurality of processors using broadcasting.

7. The computer program product of claim 5 , wherein the method further comprises:
checking whether an interrupt addressed to the target processor is pending for handling by the target processor; and
changing, based on no interrupts addressed to the target processor being pending for handling by the target processor, the interrupt blocking indicator in the first copy of the interrupt table entry assigned to the target processor to indicate the target processor is unblocked.

8. The computer program product of claim 7 , wherein the method further comprises;
continuing with the forwarding of the interrupt signal to the target processor, based on the target processor being unblocked; and
changing, based on the target processor being unblocked, the interrupt blocking indicator in the first copy of the interrupt table entry assigned to the interrupt target ID to indicate the logical processor ID being blocked, the changing being performed before the forwarding of the interrupt signal to the target processor for handling.

9. The computer program product of claim 8 , wherein the method further comprises:
retrieving, after the changing of the interrupt blocking indicator, a second copy of the interrupt table entry assigned to the interrupt target ID; and
checking the second copy of the interrupt table entry to exclude a predefined type of change of the second copy of the interrupt table entry relative to the first copy of the interrupt table entry, wherein the forwarding of the interrupt signal to the target processor for handling is based on a successful exclusion of the predefined type of change.

10. The computer program product of claim 9 , wherein the predefined type of change is a change of a first mapping in the first copy of the interrupt table entry of the interrupt target ID to a first logical processor ID relative to a second mapping of the interrupt target ID to a second logical processor ID comprised by the second copy of the interrupt table entry, wherein based on the second mapping comprising a change relative to the first mapping, the interrupt signal is forwarded for handling to the plurality of processors using broadcasting.

11. The computer program product of claim 9 , wherein the predefined type of change is a change of the first copy of the running indicator relative to a second copy of the running indicator comprised by the second copy of the interrupt table entry, wherein based on the second copy of the running indicator comprising a change relative to the first copy of the running indicator, the second copy of the running indicator indicates that the target processor is not being scheduled for usage by the guest operating system, and the interrupt signal is forwarded for handling to the plurality of processors using broadcasting.

12. The computer program product of claim 1 , wherein the method further comprises retrieving a copy of a device table entry from a device table, the device table entry comprising a direct signaling indicator to indicate whether the target processor is to be addressed directly, and wherein based on the direct signaling indicator indicating a direct forwarding of the interrupt signal, the forwarding of the interrupt signal using the logical processor ID of the target processor to address the target processor directly is executed.

13. A computer system for providing an interrupt signal to a guest operating system executed using one or more processors of a plurality of processors of the computer system, the computer system comprising:
a memory; and
at least one processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
receiving an interrupt signal with an interrupt target ID, the interrupt target ID identifying one processor of the plurality of processors as a target processor for handling the interrupt signal;
retrieving a first copy of an interrupt table entry assigned to the interrupt target ID from an interrupt table, the first copy of the interrupt table entry comprising a first copy of a running indicator to indicate whether the target processor identified by the interrupt target ID is scheduled for usage by the guest operating system;
checking, using the first copy of the running indicator, that the target processor is scheduled for usage by the guest operating system; and
translating, based on the target processor being scheduled for usage by the guest operating system, the interrupt target ID to a logical processor ID and forwarding the interrupt signal to the target processor to handle, the forwarding using the logical processor ID resulting from the translating to address the target processor directly.

14. The computer system of claim 13 , wherein the first copy of the interrupt table entry further c

Assignees

• IBM

Inventors

• Kraemer Marco
• Raisch Christoph
• Nerz Bernd
• Schmidt Donald William
• Klein Matthias
• Junghans Sascha
• Driever Peter Dana

Classifications

• G06F9/45545 Primary

  Guest-host, i.e. hypervisor is an application program itself, e.g. VirtualBox · CPC title

• G06F9/4812

  by interrupt, e.g. masked · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/5027

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

• G06F9/542

  Event management; Broadcasting; Multicasting; Notifications · CPC title