Split and duplicate ripple circuits

Patent metadata

Field	Value
Publication number	US-11733967-B2
Application number	US-202217873862-A
Country	US
Kind code	B2
Filing date	Jul 26, 2022
Priority date	Jun 22, 2020
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

Methods, systems, and devices for split and duplicate ripple circuits are described. A ripple circuit may be divided into stages, which may operate in parallel. For example, a first stage may have a finite number of possibilities for an output that is relevant for a second stage, and the second stages may be replicated according to the finite number of possibilities. The replicated second stages thus may operate concurrently with each other and the first stage, with each of the replicated second stages assuming a different possible output from the first stage. Once operation of the first stage is complete, the true output of the first stage may be used to select one of the second stages as corresponding to the correct assumed output, and the output of the selected second stage may be or may be included in a set of output signals for the circuit.

First claim

What is claimed is:

1. An apparatus, comprising:
a first set of comparators configured to generate a carry signal based at least in part on a comparison of a first subset of a first set of bits with a first subset of a second set of bits, the carry signal having one of a plurality of potential states;
a second set of comparators configured to generate a first potential set of one or more output signals based at least in part on a comparison of a second subset of the first set of bits with a second subset of the second set of bits and on a first potential state of the carry signal;
a third set of comparators configured to generate a second potential set of one or more output signals based at least in part on a comparison of the second subset of the first set of bits with the second subset of the second set of bits and on a second potential state of the carry signal; and
a selection component configured to output, based at least in part on a state of the carry signal generated by the first set of comparators, a set of one or more output signals that are based at least in part on the first potential set of one or more output signals or the second potential set of one or more output signals.

2. The apparatus of claim 1 , wherein the second set of comparators and the third set of comparators are configured to generate the first potential set of one or more output signals and the second potential set of one or more output signals, respectively, in parallel.

3. The apparatus of claim 1 , wherein the first set of comparators are configured to generate the carry signal in parallel with the generation of the first potential set of one or more output signals and the second potential set of one or more output signals.

4. The apparatus of claim 1 , wherein the third set of comparators comprises a duplicate set of the second set of comparators.

5. The apparatus of claim 1 , wherein:
the second subset of the first set of bits is more significant than the first subset of the first set of bits; and
the second subset of the second set of bits is more significant than the first subset of the second set of bits.

6. The apparatus of claim 1 , wherein a comparator of the first set of comparators is configured to compare a most significant bit (MSB) of the first subset of the first set of bits with an MSB of the first subset of the second set of bits and configured to generate the carry signal based at least in part on the comparison.

7. The apparatus of claim 1 , wherein:
the first potential state of the carry signal corresponds to a first logic value or a first voltage; and
the second potential state of the carry signal corresponds to a second logic value or a second voltage.

8. The apparatus of claim 1 , wherein the selection component is configured to select the first potential set of one or more output signals or the second potential set of one or more output signals based at least in part on the state of the carry signal, and wherein the set of one or more output signals are based at least in part on the first potential set of one or more output signals or the second potential set of one or more output signals in accordance with the selection.

9. A method, comprising:
generating, using a first set of comparators, a carry signal based at least in part on a comparison of a first subset of a first set of bits with a first subset of a second set of bits, the carry signal having one of a plurality of potential states;
generating, using a second set of comparators, a first potential set of one or more output signals based at least in part on a comparison of a second subset of the first set of bits with a second subset of the second set of bits and on a first potential state of the carry signal;
generating, using a third set of comparators, a second potential set of one or more output signals based at least in part on a comparison of the second subset of the first set of bits with the second subset of the second set of bits and on a second potential state of the carry signal; and
selecting between at least the first potential set of one or more output signals and the second potential set of one or more output signals using a selection component, based at least in part on the generated carry signal.

10. The method of claim 9 , wherein generating the first potential set of one or more output signals occurs in parallel with generating the second potential set of one or more output signals.

11. The method of claim 9 , wherein generating the carry signal occurs in parallel with generating the first potential set of one or more output signals and generating the second potential set of one or more output signals.

12. The method of claim 9 , wherein the third set of comparators is a duplicate set of the second set of comparators.

13. The method of claim 9 , wherein generating the carry signal comprises:
comparing, using a comparator of the first set of comparators, a most significant bit (MSB) of the first subset of the first set of bits with an MSB of the first subset of the second set of bits, the carry signal generated based at least in part on the comparison.

14. The method of claim 9 , wherein:
the second subset of the first set of bits is more significant than the first subset of the first set of bits; and
the second subset of the second set of bits is more significant than the first subset of the second set of bits.

15. An apparatus, comprising:
a set of memory cells; and
a controller coupled with the set of memory cells, wherein the controller is configured to cause the apparatus to:
generate, using a first set of comparators, a carry signal based at least in part on a comparison of a first subset of a first set of bits with a first subset of a second set of bits, the carry signal having one or a plurality of potential states;
generate, using a second set of comparators, a first potential set of one or more output signals based at least in part on a comparison of a second subset of the first set of bits with a second subset of the second set of bits and on a first potential state of the carry signal;
generate, using a third set of comparators, a second potential set of one or more output signals based at least in part on a comparison of the second subset of the first set of bits with the second subset of the second set of bits and a second potential state of the carry signal; and
select between at least the first potential set of one or more output signals and the second potential set of one or more output signals using a selection component, based at least in part on the generated carry signal.

16. The apparatus of claim 15 , wherein the first potential set of one or more output signals are generated in parallel with the generation of the second potential set of one or more output signals.

17. The apparatus of claim 15 , wherein the carry signal is generated in parallel with the generation of the first potential set of one or more output signals and the generation of the second potential set of one or more output signals.

18. The apparatus of claim 15 , wherein the third set of comparators is a duplicate set of the second set of comparators.

19. The apparatus of claim 15 , wherein, to generate the carry signal, the controller is configured to cause the apparatus to:
compare, using a comparator of the first set of comparators, a most significant bit (MSB) of the first subset of the first set of bits with an MSB of the first subset of the second set of bits, the carry signal generated based at least in part on the comparison.

Assignees

• Micron Technology Inc
• Micron Technoloay Inc

Inventors

• Morgan Donald Martin

Classifications

• G06F7/501 Primary

  Half or full adders, i.e. basic adder cells for one denomination · CPC title

• G06F7/02

  Comparing digital values (G06F7/06, {G06F7/22,} G06F7/38 take precedence) · CPC title

• G06F7/026

  Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator · CPC title

• G06F7/503

  using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal · CPC title

• G06F7/507

  using selection between two conditionally calculated carry or sum values · CPC title