Lossless pixel compression based on inferred control information

Patent metadata

Field	Value
Publication number	US-11729403-B2
Application number	US-201716647998-A
Country	US
Kind code	B2
Filing date	Dec 5, 2017
Priority date	Dec 5, 2017
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

A lossless pixel compressor may include technology to detect a format of a pixel memory region, and compress the pixel memory region together with embedded control information which indicates the detected format of the pixel memory region. Other embodiments are disclosed and claimed.

First claim

We claim:

1. A semiconductor package apparatus, comprising:
a substrate; and
logic coupled to the substrate, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the substrate to:
detect a format of a pixel memory region based on an analysis of the pixel memory region, and
compress the pixel memory region together with embedded control information which indicates the detected format of the pixel memory region.

2. The apparatus of claim 1 , wherein the logic is further to:
determine compression results for two or more compression techniques;
select one of the two or more compression techniques based on the determined compression results; and
compress the pixel memory region using the selected compression technique together with the embedded control information.

3. The apparatus of claim 2 , wherein the logic is further to:
compress a portion of the pixel memory region using one of the two or more compression techniques; and
estimate the compression results for the entire pixel memory region based on a compression result for the compressed portion of the pixel memory region.

4. The apparatus of claim 2 , wherein the logic is further to:
compare a compression result for one of the two or more compression techniques against a threshold; and
select one of the two or more compression techniques based on the threshold comparison.

5. The apparatus of claim 1 , wherein the logic is further to:
sub-divide cachelines into sub-regions which are independently compressible.

6. The apparatus of claim 1 , wherein the logic is further to:
sub-divide cachelines into sub-regions which are independently decompres sable.

7. The apparatus of claim 1 , wherein the logic is further to:
rearrange bytes of the pixel memory region into sub-regions based on the detected pixel format.

8. The apparatus of claim 1 , wherein the logic is further to:
detect a depth of the pixel memory region.

9. The apparatus of claim 1 , wherein the embedded control information includes an index to a multi-level applied compression table.

10. A method of compressing pixels, comprising:
detecting a format of a pixel memory region; and
compressing the pixel memory region together with embedded control information which indicates the detected format of the pixel memory region.

11. The method of claim 10 , further comprising:
determining compression rates for two or more compression techniques;
selecting one of the two or more compression techniques based on the determined compression rates; and
compressing the pixel memory region using the selected compression technique together with the embedded control information.

12. The method of claim 11 , further comprising:
compressing a portion of the pixel memory region using one of the two or more compression techniques; and
estimating compression rates for the entire pixel memory region based on a compression rate for the compressed portion of the pixel memory region.

13. The method of claim 11 , further comprising:
comparing a compression rate for one of the two or more compression techniques against a threshold; and
selecting one of the two or more compression techniques based on the threshold comparison.

14. The method of claim 10 , further comprising:
sub-dividing cachelines into sub-regions which are independently compressible.

15. The method of claim 10 , further comprising:
sub-dividing cachelines into sub-regions which are independently decompressable.

16. The method of claim 10 , further comprising:
rearranging bytes of the pixel memory region into sub-regions based on the detected pixel format.

17. The method of claim 10 , further comprising:
detecting a depth of the pixel memory region.

18. The method of claim 10 , wherein the embedded control information includes an index to a multi-level applied compression table.

19. At least one non-transitory computer readable medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to:
detect a format of a pixel memory region; and
compress the pixel memory region together with embedded control information which indicates the detected format of the pixel memory region.

20. The at least one non-transitory computer readable medium of claim 19 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
determine compression results for two or more compression techniques;
select one of the two or more compression techniques based on the determined compression results; and
compress the pixel memory region using the selected compression technique together with the embedded control information.

21. The at least one non-transitory computer readable medium of claim 20 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
compress a portion of the pixel memory region using one of the two or more compression techniques; and
estimate the compression results for the entire pixel memory region based on a compression result for the compressed portion of the pixel memory region.

22. The at least one non-transitory computer readable medium of claim 20 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
comparing a compression result for one of the two or more compression techniques against a target compression rate; and
selecting one of the two or more compression techniques based on the target compression rate comparison.

23. The at least one non-transitory computer readable medium of claim 19 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
sub-divide cachelines into sub-regions which are independently compressible.

24. The at least one non-transitory computer readable medium of claim 19 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
sub-divide cachelines into sub-regions which are independently decompressable.

25. The at least one non-transitory computer readable medium of claim 19 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
rearrange bytes of the pixel memory region into sub-regions based on the detected pixel format.

Assignees

• Intel Corp

Inventors

• Holland James
• CHAN Hiu-Fai
• Fu Fangwen
• Xu Qian
• Lee Sang-Hee
• Krishnan Vidhya

Classifications

• H04N19/182 Primary

  the unit being a pixel · CPC title

• H04N19/423

  characterised by memory arrangements (H04N19/433 takes precedence) · CPC title

• H04N1/64 Primary

  Systems for the transmission or the storage of the colour picture signal; Details therefor, e.g. coding or decoding means therefor {(H04N19/00 takes precedence)} · CPC title

• H04N19/426

  using memory downsizing methods · CPC title

• H04N19/433

  characterised by techniques for memory access · CPC title