Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits

Patent metadata

Field	Value
Publication number	US-11727260-B2
Application number	US-202117484828-A
Country	US
Kind code	B2
Filing date	Sep 24, 2021
Priority date	Sep 28, 2018
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

First claim

The invention claimed is:

1. An apparatus, comprising:
a network interface;
a peripheral controller;
a main memory; and,
a semiconductor chip having a compute-in-memory (CIM) circuit to implement a neural network, the CIM circuit comprising a mathematical computation circuit coupled to a memory array, the mathematical computation circuit comprising a switched capacitor circuit, the switched capacitor circuit comprising a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within metal/dielectric layers of the semiconductor chip.

2. The apparatus of claim 1 wherein the memory array comprises a static random access memory (SRAM) memory array.

3. The apparatus of claim 2 wherein the BEOL capacitor and thin film transistor are located above the SRAM memory array.

4. The apparatus of claim 3 wherein the mathematical computation circuit is to accumulate values read from the memory array.

5. The apparatus of claim 3 wherein the mathematical computation circuit is to multiply and accumulate values read from the memory array.

6. The apparatus of claim 1 wherein the mathematical computation circuit is to accumulate values read from the memory array.

7. The apparatus of claim 1 wherein the mathematical computation circuit is to multiply and accumulate values read from the memory array.

8. An apparatus, comprising:
a network interface;
a peripheral controller;
a main memory; and,
a semiconductor chip having a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip, the CIM circuit comprising a mathematical computation circuit coupled to a memory array, the mathematical computation circuit comprising an accumulation circuit, the accumulation circuit comprising a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

9. The apparatus of claim 8 wherein the memory array comprises a static random access memory (SRAM) memory array.

10. The apparatus of claim 9 wherein the ferroelectric BEOL capacitor is located above the SRAM memory array.

11. The apparatus of claim 10 wherein the mathematical computation circuit is to accumulate values read from the memory array.

12. The apparatus of claim 10 wherein the mathematical computation circuit is to multiply and accumulate values read from the memory array.

13. The apparatus of claim 8 wherein the mathematical computation circuit is to accumulate values read from the memory array.

14. The apparatus of claim 8 wherein the mathematical computation circuit is to multiply and accumulate values read from the memory array.

15. The apparatus of claim 8 wherein ferroelectric material of the ferroelectric BEOL capacitor comprises grain sizes less than 3 nm and/or is amorphous.

16. The apparatus of claim 8 wherein the ferroelectric BEOL capacitor comprises material selected from the group consisting of:
hafnium zirconium oxide;
hafnium oxide;
zirconium oxide;
hafnium aluminum oxide;
hafnium silicon oxide;
hafnium zirconium aluminum oxide;
hafnium zirconium silicon oxide;
hafnium yttrium oxide;
yttrium zirconium oxide;
hafnium yttrium zirconium oxide.

17. The apparatus of claim 16 wherein the material is doped with yttrium.

18. The apparatus of claim 8 wherein the CIM circuit further comprises a switched capacitor circuit that comprises a circuit to sense a switch in dipole moment direction of the ferroelectric BEOL capacitor, wherein, the sense of the switch is to determine an accumulate value.

19. The apparatus of claim 18 wherein the circuit is a current sensing circuit.

Assignees

• Intel Corp

Inventors

• Sharma Abhishek
• Kavalieros Jack T
• Young Ian A
• Krishnamurthy Ram
• Manipatruni Sasikanth
• Avci Uygar
• Chen Gregory K
• Mathuriya Amrita
• Kumar Raghavan
• Knag Phil
• Sumbul Huseyin Ekin
• Haratipour Nazila
• Le Van H

Classifications

• G06N3/04

  Architecture, e.g. interconnection topology · CPC title

• G06N3/0499

  Feedforward networks · CPC title

• G06N3/065 Primary

  Analogue means · CPC title

• G06F17/16

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title