Isolated gate driver device for a power electrical system and corresponding power electrical system

Patent metadata

Field	Value
Publication number	US-11722133-B2
Application number	US-202217807519-A
Country	US
Kind code	B2
Filing date	Jun 17, 2022
Priority date	Jun 30, 2021
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

In an embodiment an isolated gate driver device includes a low-voltage section having a control input configured to receive a PWM control signal with a switching frequency from a control stage, a high-voltage section, galvanically isolated from the low-voltage section the high-voltage section including a driving output configured to provide a gate-driving signal as a function of the PWM control signal to a power stage having at least one switch, a feedback input configured to receive at least one feedback signal indicative of an operation of the power stag, and an ADC module configured to convert the feedback signal into a digital data stream and a conversion-control module coupled to the ADC module and configured to provide a conversion-trigger signal designed to determine a start of a conversion for acquiring a new sample of the feedback signal.

First claim

What is claimed is:

1. An isolated gate driver device comprising:
a low-voltage section having a control input configured to receive a PWM control signal with a switching frequency from a control stage;
a high-voltage section galvanically isolated from the low-voltage section, the high-voltage section comprising:
a driving output configured to provide a gate-driving signal as a function of the PWM control signal to a power stage having at least one switch;
a feedback input configured to receive at least one feedback signal indicative of an operation of the power stage;
an ADC module configured to convert the feedback signal into a digital data stream; and
a conversion-control module coupled to the ADC module and configured to provide a conversion-trigger signal designed to determine a start of a conversion for acquiring a new sample of the feedback signal; and

a communication channel configured to:
provide an isolated communication between the low-voltage section and the high-voltage section, and
send the digital data stream to the low-voltage section to be fed back to the control stage.

2. The device according to claim 1 , wherein the conversion-control module comprises:
an acquisition block configured to acquire a signal indicative of an operating status, either ON or OFF, at the driving output and to provide a status signal indicative of the operating status;
a timer block configured to receive the status signal from the acquisition block and measure a duration of an ON interval and an OFF interval associated with the operating status; and
a control-logic block configured to generate the conversion-trigger signal as a function of the duration of the ON interval and the OFF interval and as a function of the status signal.

3. The device according to claim 2 , wherein the new sample of the feedback signal is acquired at each period of the PWM control signal.

4. The device according to claim 2 ,
wherein the acquisition block is configured to:
acquire a value of a gate-to-source voltage associated with the switch ( 18 ), and
compare the value with a threshold value so as to detect ON and OFF transitions of the switch and consequently the operating status, and

wherein the timer block is configured to reset at each of the transitions so as to measure the duration of the ON and OFF intervals.

5. The device according to claim 2 , wherein the conversion-control module further comprises a first register coupled to the timer block, the first register configured to store the duration of the ON interval, and a second register, coupled to the timer block, the second register configured to store the duration of the OFF interval.

6. The device according to claim 2 , wherein the control-logic block is configured to determine the start of the conversion at a centre of the ON interval when the duration of the ON interval is compatible with a conversion time implemented by the ADC module for acquiring the new sample of the feedback signal, or at a centre of the OFF interval when the duration of the ON interval is not compatible with the conversion time.

7. The device according to claim 6 , wherein the control-logic block is configured to determine the start of the conversion:
at the centre of the ON interval (T ON ) when T ON >T CONV +T GUARD ,
at the centre of the OFF interval (T OFF ) when T ON ≤T CONV +T GUARD , and
wherein T GUARD is a guard-time interval, T ON is the duration of the ON interval, T OFF is the duration of the OFF interval, and T CONV is the duration of the conversion time.

8. The device according to claim 1 , wherein the high-voltage section comprises a first interface module configured to receive the digital data stream from the ADC module for transmission to the communication channel.

9. The device according to claim 8 , wherein the first interface module comprises a first accumulator block configured to accumulate a number of samples resulting from analog-to-digital conversions by the ADC module so as to match a frequency of the PWM control signal to a different communication frequency associated with the communication channel.

10. The device according to claim 9 , wherein the first accumulator block is configured to be reset whenever a request for data arrives from the communication channel.

11. The device according to claim 1 , wherein the low-voltage section comprises a second interface module configured to receive the digital data stream from the communication channel and a PWM generator block configured to generate feedback output signals at an output frequency to be sent to the control stage.

12. The device according to claim 11 , wherein the second interface module comprises a second accumulator block configured to accumulate a number of samples transmitted over the communication channel in order to match the output frequency to a different communication frequency associated with the communication channel.

13. The device according to claim 12 , wherein the second accumulator block is configured to be reset at each new period of the feedback output signal generated by the PWM generator block.

14. The device according to claim 12 , wherein the output frequency of the feedback output signals generated by the PWM generator block is fixed, and a corresponding duty-cycle is determined by an average content of the second accumulator block.

15. The device according to claim 1 , wherein the high-voltage section and the low-voltage section comprise, respectively, a first integrity check block and a second integrity check block, which are coupled to the communication channel and are configured to check integrity of the data transmitted over the communication channel.

16. The device according to claim 1 , wherein the communication channel is of a half-duplex type with capacitive-coupling.

17. The device according to claim 1 , wherein the ADC module is a sigma-delta converter with conversion time of less than half of a switching period, given by an inverse of the switching frequency.

18. An electrical system comprising:
the isolated gate driver device according to claim 1 ,
wherein the control stage comprises a PWM controller configured to generate the PWM control signals as a function of a desired control strategy of the power stage, and a reading interface configured to receive feedback output signals, and
wherein the power stage comprises at least one power switch configured to be driven in a switching mode to obtain a power transfer and has a respective gate terminal coupled to the driving output so as to receive the gate-driving signal.

Assignees

• St Microelectronics Srl

Inventors

• D'Angelo Vittorio
• Cannavacciuolo Salvatore
• Bendotti Valerio
• Selvo Paolo
• Alagna Diego

Classifications

• H03K17/567 Primary

  Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT · CPC title

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03K7/08

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title

• H03K17/689

  with galvanic isolation between the control circuit and the output circuit (H03K17/78 takes precedence) · CPC title