High-resolution current and method for generating a current

Patent metadata

Field	Value
Publication number	US-9705485-B1
Application number	US-201615208071-A
Country	US
Kind code	B1
Filing date	Jul 12, 2016
Priority date	Jul 13, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A circuit for generating an output current and a method for generating an output current are provided. A voltage generator circuit is configured to generate at least two voltages. A digital circuit is configured to generate a pulse width modulation signal having a waveform characteristic that is controllable based on bits of configuration data received by the digital circuit. An averaging circuit is configured to receive the pulse width modulation signal and generate a bias voltage that comprises a weighted average of the at least two voltages. Weights of the at least two voltages are based on the waveform characteristic of the pulse width modulation signal. A voltage-controlled current source is configured to generate an output current based on the bias voltage.

First claim

What is claimed is:

1. A circuit for generating an output current, the circuit comprising:
a voltage generator circuit configured to generate at least two voltages;
a digital circuit configured to generate a pulse width modulation signal having a waveform characteristic that is controllable based on bits of configuration data received by the digital circuit;
an averaging circuit configured to (i) receive the pulse width modulation signal, and (ii) generate a bias voltage that comprises a weighted average of the at least two voltages, weights of the at least two voltages being based on the waveform characteristic of the pulse width modulation signal; and
a voltage-controlled current source configured to generate an output current based on the bias voltage.

2. The circuit of claim 1 , wherein the at least two voltages comprise a first voltage and a second voltage, and wherein the output current has a generally linear relationship with the bias voltage for bias voltages between the first voltage and the second voltage.

3. The circuit of claim 1 , wherein the waveform characteristic is a duty cycle.

4. The circuit of claim 1 , further comprising a constant current source configured to generate a reference current, wherein the voltage generator circuit comprises:
a first transistor configured to draw the reference current from the constant current source;
a second transistor configured to draw a first current equal to the reference current multiplied by a first multiplicative factor, the first and second transistors being connected to form a first current mirror; and
a third transistor configured to draw a second current equal to the reference current multiplied by a second multiplicative factor that is different from the first multiplicative factor, the first and third transistors being connected to form a second current mirror, wherein a first voltage of the at least two voltages is based on the first current, and a second voltage of the at least two voltages is based on the second current.

5. The circuit of claim 4 , wherein the output current comprises a weighted average of the first and second currents, weights of the respective first and second currents being based on the waveform characteristic of the pulse width modulation signal.

6. The circuit of claim 4 , wherein the voltage generator circuit further comprises:
a fourth transistor coupled to the second transistor and configured to draw the first current, wherein a voltage at a gate terminal of the fourth transistor is based on the first current and comprises the first voltage; and
a fifth transistor coupled to the third transistor and configured to draw the second current, wherein a voltage at a gate terminal of the fifth transistor is based on the second current and comprises the second voltage.

7. The circuit of claim 1 , wherein the averaging circuit is configured to receive the at least two voltages, the averaging circuit comprising:
a low-pass filter comprising an input node and an output node; and
a coupling circuit that is responsive to the pulse width modulation signal, the coupling circuit being configured to (i) couple a first voltage of the at least two voltages to the input node when the pulse width modulation signal has a first logic level, and (ii) couple a second voltage of the at least two voltages to the input node when the pulse width modulation signal has a second logic level that is different from the first logic level, wherein a voltage at the output node of the low-pass filter comprises the bias voltage.

8. The circuit of claim 7 , wherein the coupling circuit comprises:
a first switch configured to receive the first voltage, wherein the first switch (i) couples the first voltage to the input node when the pulse width modulation has the first logic level, and (ii) decouples the first voltage from the input node when the pulse width modulation signal has the second logic level; and
a second switch configured to receive the second voltage, wherein the second switch (i) couples the second voltage to the input node when the pulse width modulation has the second logic level, and (ii) decouples the second voltage from the input node when the pulse width modulation signal has the first logic level.

9. The circuit of claim 7 , wherein the low-pass filter comprises:
a resistor coupled between the input node and the output node; and
a capacitor coupled between the output node and a ground reference voltage, wherein the resistor and capacitor form a resistor-capacitor (RC) circuit having a cutoff frequency, the RC circuit blocking frequency components above the cutoff frequency.

10. The circuit of claim 1 , wherein the digital circuit receives a digital clock signal, the digital circuit comprising:
a digital state machine responsive to edges in the digital clock signal, the digital state machine being configured to (i) maintain a count value between a predetermined minimum value and a predetermined maximum value, the count value being incremented in response to edges of the digital clock signal, (ii) assert the pulse width modulation signal having a first logic level when the count value is within a first range of count values, and (iii) assert the pulse width modulation signal having a second logic level when the count value is within a second range of count values, the first and second ranges being based on the bits of configuration data.

11. The circuit of claim 1 , wherein the voltage-controlled current source comprises:
a transistor that receives the bias voltage at a gate terminal, a current flow between source and drain terminals of the transistor being equal to the output current.

12. A circuit for generating an output current, the circuit comprising:
a voltage generator circuit configured to generate at least two voltages;
a pulse width modulation circuit configured to generate a pulse width modulation signal having a waveform characteristic that is controllable based on bits of configuration data;
an averaging circuit configured to generate a bias voltage that comprises a weighted average of the at least two voltages, weights of the at least two voltages being based on the waveform characteristic of the pulse width modulation signal; and
a current source configured to generate an output current based on the bias voltage.

13. The circuit of claim 12 , wherein the pulse width modulation circuit comprises:
an interface for receiving the bits of configuration data from a device that is coupled to the pulse width modulation circuit; and
a storage device for storing the bits of configuration data.

14. The circuit of claim 12 , further comprising a second current source configured to generate a reference current, wherein the voltage generator circuit comprises:
a first transistor configured to draw the reference current from the second current source;
a second transistor configured to draw a first current equal to the reference current multiplied by a first multiplicative factor, the first and second transistors being connected to form a first current mirror; and
a third transistor configured to draw a second current equal to the reference current multiplied by a second multiplicative factor that is different from the first multiplicative factor, the first and third transistors being connected to form a second current mirror, wherein a first voltage of the at least two voltages is based on the first current, and a second voltage of the at least two voltages is based on the second current.

15. The circuit of claim 14 , wherein the voltage generator circuit further comprises:
a fourth transistor coupled to the second

Assignees

• Marvell Israel (M I S L) Ltd
• Marvell Israel (M I S L) Ltd

Inventors

• Finfter Itai

Classifications

• H03K7/08 Primary

  Duration or width modulation {; Duty cycle modulation} · CPC title

• G05F3/16

  being semiconductor devices · CPC title

• G05F3/262

  using field-effect transistors only · CPC title