Power converter with charge injection from booster rail

Patent metadata

Field	Value
Publication number	US-11722060-B2
Application number	US-202016936410-A
Country	US
Kind code	B2
Filing date	Jul 22, 2020
Priority date	Jul 22, 2020
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

A converter circuit, included in a power converter circuit, may generate a given voltage level on a regulated power supply node of a computer system. A control circuit may monitor a voltage level and assert a control signal in response to a determination that a regulation event has occurred. A boost converter circuit, included in the power converter circuit, may inject charge into to the regulated power supply node via a capacitor, in response to an assertion of the control signal.

First claim

What is claimed is:

1. An apparatus, comprising:
a first power converter circuit coupled to a regulated power supply node, wherein the first power converter circuit is configured to generate a given voltage level on the regulated power supply node using a voltage level of an input power supply node and a reference voltage, wherein the voltage level of the input power supply node is positive relative to a ground reference;
a second power converter circuit that includes an inductor connected, in series via a boost node, to a capacitor, wherein the capacitor is coupled to the regulated power supply node, and wherein the second power converter circuit is configured to:
couple a terminal of the inductor to the input power supply node to source current from the input power supply node to the regulated power supply node for a first duration during which a control signal is asserted; and
pre-charge, for a second duration during which the control signal is de-asserted, the boost node to voltage level that is negative relative to the ground reference;

a load circuit coupled to the regulated power supply node, wherein the load circuit is configured to generate an activation signal in anticipation of an increase in a level of activity of the load circuit, wherein the activation signal includes information indicative of an anticipated level of activity; and
a control circuit configured to:
receive the activation signal from the load circuit; and
assert the control signal in response to a determination that the anticipated level of activity is greater than an activity threshold.

2. The apparatus of claim 1 , wherein the control circuit is further configured to:
monitor a voltage level of the regulated power supply node; and
assert the control signal in response to a determination that the voltage level of the regulated power supply node is less than a threshold value.

3. The apparatus of claim 1 , wherein the control circuit is further configured to de-assert the control signal in response to a determination that the activation signal has been de-asserted.

4. The apparatus of claim 1 , wherein the first power converter circuit includes a plurality of phase circuits coupled to the regulated power supply node via respective ones of a plurality of inductors, and wherein the plurality of phase circuits are configured to source respective currents to the regulated power supply node via the respective ones of the plurality of inductors.

5. The apparatus of claim 1 , wherein the load circuit is a component of a system-on-a-chip (SoC).

6. The apparatus of claim 1 , wherein the first power converter circuit is included on a first integrated circuit, wherein the load circuit is included on a second integrated circuit, and wherein the second power converter circuit is included on a third integrated circuit.

7. The apparatus of claim 6 , wherein the second integrated circuit further includes a switch circuit that includes a plurality of capacitors coupled to the regulated power supply node and corresponding ones of a plurality of switches configured to couple, based on a plurality of switch control signals, respective ones of the plurality of capacitors to the boost node to adjust an amount of capacitance between the regulated power supply node and the boost node.

8. A method, comprising:
generating, by a first converter circuit coupled to a regulated power supply node, a given voltage level on the regulated power supply node using a voltage level of an input power supply node that is positive relative to a ground reference;
asserting, by a load circuit coupled to the regulated power supply node, an activation signal in response to determining a level of activity of the load circuit is increasing, wherein the activation signal include information indicative of the level of activity of the load circuit;
in response to determining that the level of activity is greater than an activity threshold, asserting a control signal by a control circuit; and
coupling, by a second converter circuit for a first duration that the activation signal is asserted, a terminal of an inductor included in the second converter circuit to the input power supply node, wherein the inductor is connected, in series via a boost node to a capacitor coupled to the regulated power supply node;
sourcing, by the second converter circuit for the first duration, current from the input power supply node to the regulated power supply node via the inductor; and
pre-charging, by the second converter circuit for a second duration during which the control signal is de-asserted, the boost node to a pre-charge voltage level that is negative relative to the ground reference.

9. The method of claim 8 , wherein the load circuit is a component of a system-on-a-chip (SoC).

10. The method of claim 8 , further comprising monitoring, by the control circuit, the regulated power supply node by comparing a voltage level of the regulated power supply node to a threshold value.

11. The method of claim 10 , further comprising asserting the control signal in response to determining that the voltage level of the regulated power supply node is less than the threshold value.

12. The method of claim 8 , wherein the first converter circuit includes a plurality of phase circuits, and wherein generating, by the first converter circuit, the given voltage level on the regulated power supply node includes sourcing, by the plurality of phase circuits, respective charge currents during respective charge time periods.

13. The method of claim 12 , wherein generating, by the first converter circuit, the given voltage level on the regulated power supply node includes circulating, by the plurality of phase circuits, respective discharge currents from the regulated power supply node during respective discharge time periods.

14. An apparatus, comprising:
a primary power converter circuit coupled to a regulated power supply node, wherein the primary power converter circuit is configured to generate a given voltage level on the regulated power supply node using a voltage level of an input power supply node and a reference voltage;
a boost power converter circuit that includes an inductor connected, in series via a boost node, to a capacitor, wherein the capacitor is coupled to the regulated power supply node, and wherein the boost power converter circuit is configured to couple a terminal of the inductor to the input power supply node to source current from the input power supply node to the regulated power supply node in response to an assertion of a control signal;
a load circuit coupled to the regulated power supply node, wherein the load circuit is configured to assert a digital activation signal in anticipation of an increase in a level of activity, wherein the digital activation signal includes information indicative of an anticipated level of activity; and
a control circuit configured to:
receive the digital activation signal from the load circuit; and
assert the control signal in response to a determination that the anticipated level of activity is greater than an activity threshold.

15. The apparatus of claim 14 , wherein the primary power converter circuit is further configured to:
perform a comparison of a voltage level of the regulated power supply node to a threshold value; and
generate the control signal using a result of the comparison.

16. The apparatus of claim 14 , wherein the control circuit is further configured to:
perform a comparison of a voltage level of the regulated power supply node to a threshold value; and
generate the control signal using a resul

Assignees

• Apple Inc

Inventors

• Zyuban Victor
• Rohrer Norman J
• Searles Shawn

Classifications

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H03K5/24 Primary

  the characteristic being amplitude · CPC title