Memory device capable of outputting fail data in parallel bit test and memory system including the memory device

Patent metadata

Field	Value
Publication number	US-11721408-B2
Application number	US-202117388238-A
Country	US
Kind code	B2
Filing date	Jul 29, 2021
Priority date	Nov 4, 2020
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

A memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into multiple regions. The test controller is configured to perform a parallel bit test (PBT) on the plurality of memory cells, where the test controller selects fail data including a fail data bit among internal data output from the multiple regions during the PBT, and outputs the fail data via a data input/output signal line to the outside of the memory device.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell array comprising a plurality of memory cells, wherein the memory cell array is divided into multiple regions; and
a test controller configured to perform a parallel bit test (PBT) on the plurality of memory cells, wherein the test controller receives internal data from the multiple regions during the PBT, generates one or more select signals based on the internal data, generates fail data comprising a fail data bit indicating a region from the multiple regions based on the internal data and one or more select signals, and outputs the fail data via a data input/output signal line to the outside of the memory device.

2. The memory device of claim 1 , wherein the memory cell array is divided into first through fourth regions, and
wherein, when at least one data bit among first through fourth internal data output by a corresponding one of the first through fourth regions is output in a logic state that is different from another data bit among the first through fourth internal data, the test controller specifies the at least one data bit as the fail data bit.

3. The memory device of claim 2 , wherein the test controller comprises:
a select signal generator circuit configured to generate a first select signal by performing XOR logic computation on the first internal data and the second internal data, and a second select signal by performing XOR logic computation on the second internal data and the third internal data; and
a selector circuit configured to input the first through fourth internal data, and select and output, as an output data, the fail data including the fail data bit among the first through fourth internal data.

4. The memory device of claim 3 , wherein the selector circuit is configured with a multiplexer,
wherein the multiplexer comprises:
a first input to which a fourth internal data line is connected;
a second input to which a third internal data line is connected;
a third input to which a first internal data line is connected;
a fourth input to which a second internal data line is connected;
a first select signal input to which a first select signal line is connected;
a second select signal input to which a second select signal line is connected; and

an output configured to output the output data, and
wherein the first to fourth internal data lines transmit the first to fourth internal data, respectively, and the first and second select signal lines transmit the first and second select signals, respectively.

5. The memory device of claim 2 , wherein the test controller outputs a first voltage level to the outside of the memory device via the data input/output signal line, when the fail data bit is not specified among the first through fourth internal data and the fail data is not output, and
the first voltage level is a voltage level that does not correspond to either a first logic state of the first through fourth internal data or a second logic state opposite to the first logic state.

6. The memory device of claim 5 , wherein the first voltage level is an intermediate level between a voltage level of the first logic state and a voltage level of the second logic state.

7. The memory device of claim 5 , wherein the test controller comprises:
a first select signal generator circuit configured to generate a first select signal by performing XOR logic computation on the first internal data and the second internal data, and a second select signal by performing XOR logic computation on the second internal data and the third internal data;
a first selector circuit configured to input the first through fourth internal data, and select and output, as a first output data, the fail data including the fail data bit among the first through fourth internal data;
a second select signal generator circuit configured to generate a third select signal based on the first through fourth internal data; and
a second selector circuit configured to input the first output data and the first voltage level of the first selector circuit, and select and output, as a second output data, one of the first output data and the first voltage level in response to the third select signal.

8. The memory device of claim 7 , wherein the first selector circuit is configured with a first multiplexer,
wherein the first multiplexer comprises:
a first input to which a fourth internal data line is connected;
a second input to which a third internal data line is connected;
a third input to which a first internal data line is connected;
a fourth input to which a second internal data line is connected;
a first select signal input to which a first select signal line is connected;
a second select signal input to which a second select signal line is connected; and

an output configured to output the first output data, and
wherein the first to fourth internal data lines transmit the first to fourth internal data, respectively, and the first and second select signal lines transmit the first and second select signals, respectively.

9. The memory device of claim 7 , wherein the second select signal generator circuit comprises:
a first XOR logic circuit configured to receive the first internal data and the second internal data;
a second XOR logic circuit configured to receive the third internal data and the fourth internal data;
a first XNOR logic circuit configured to receive the first internal data and the third internal data;
a second XNOR logic circuit configured to receive the second internal data and the fourth internal data; and
an AND logic circuit configured to receive an output of the first XOR logic circuit, an output of the second XOR logic circuit, an output of the first XNOR logic circuit, and an output of the second XNOR logic circuit, and output the third select signal.

10. The memory device of claim 7 , wherein the second selector circuit is configured with a second multiplexer,
wherein the second multiplexer comprises:
a first input to which a first output data line of the first selector circuit is connected;
a second input to which a first voltage level line is connected;
a third select signal input to which a third select signal line is connected; and
an output configured to output the second output data, and
wherein the first output data line transmits the first output data, the first voltage level line transmits the first voltage level, and the third select signal line transmits the third select signal.

11. A memory system comprising:
a plurality of memory devices coupled to a printed circuit board, and each comprising a memory cell array comprising a plurality of memory cells and a test controller, wherein the memory cell array is divided into multiple regions; and
a memory controller configured to control the plurality of memory devices, and comprising an error correction code (ECC) engine configured to correct and detect an error of data read from the plurality of memory devices,
wherein, in each of the plurality of memory devices, the test controller performs a parallel bit test (PBT) on the multiple regions of the memory cell array, receives internal data from the multiple regions during the PBT, generates one or more select signals based on the internal data, generates fail data comprising a fail data bit indicating a region from the multiple regions based on the internal data and one or more select signals, and outputs the fail data to the memory controller via a data input/output signal line, and
the memory controller corrects the fail data bit of the fail data by using the ECC engine.

12. The memory system of claim 11 , wherein the ECC engine generat

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Daejeong
• Kim Namhyung
• Kim Dohan
• Seo Deokho
• Shin Wonjae
• CHOI Insu

Classifications

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C29/50004

  of threshold voltage · CPC title

• G11C2029/5004

  Voltage · CPC title

• G11C11/4063 Primary

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing · CPC title