Partial chip, and systems having the same

Patent metadata

Field	Value
Publication number	US-9508452-B2
Application number	US-201514603452-A
Country	US
Kind code	B2
Filing date	Jan 23, 2015
Priority date	Jan 23, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A partial chip and a system including the partial chip are provided. The partial chip includes a memory cell array and a signal control circuit. The memory cell array includes a pass region and a fail region. The signal control circuit is configured to generate second data corresponding to first data to be output from the fail region.

First claim

What is claimed is:

1. A partial chip comprising:
a memory cell array including a pass region and a fail region; and
a signal control circuit configured to generate second data corresponding to first data to be output from the fail region, wherein the signal control circuit is configured to bypass third data output from the pass region to a data comparison circuit in the partial chip.

2. The partial chip of claim 1 , wherein the second data is generated during a parallel bit test (PBT) operation and all of the second data is set to one of a logic high and a logic low by using the signal control circuit.

3. The partial chip of claim 2 , further comprising a mode register which includes information on performance of the PBT operation.

4. The partial chip of claim 1 , further comprising a partial chip control circuit configured to set the pass region to be a logic high and the fail region to be a logic low.

5. The partial chip of claim 1 , wherein the partial chip is a dynamic random access memory (DRAM).

6. A memory module comprising:
a printed circuit board (PCB) including a plurality of connection pins; and
the partial chip of claim 1 mounted on the PCB.

7. The memory module of claim 6 , wherein the signal control circuit is configured to set all of the second data to be one of a logic high and a logic low during a parallel bit test (PBT) operation.

8. The memory module of claim 7 , wherein the partial chip further includes a mode register including information on performance of the PBT operation, wherein the partial chip is a dynamic random access memory (DRAM), and wherein the partial chip further includes a partial chip control circuit configured to set the pass region to be the logic high and to set the fail region to be the logic low.

9. A system comprising:
the memory module of claim 6 ;
a memory module slot connected to the memory module; and
a processor electrically connected to the memory module slot,
wherein the processor includes a memory controller configured to control an operation of the partial chip.

10. The system of claim 9 ,
wherein the signal control circuit is configured to set all of the second data to be one of a logic high and a logic low during a parallel bit test (PBT) operation.

11. The system of claim 10 , wherein the partial chip further includes a mode register having information on performance of the PBT operation,
wherein the partial chip is a dynamic random access memory (DRAM),
wherein the partial chip further includes a partial chip control circuit configured to set the pass region to the logic high and the fail region to be the logic low.

12. A system comprising:
the partial chip of claim 1 ;
a card interface; and
a memory controller configured to control data exchange between the partial chip and the card interface.

13. The system of claim 12 ,
wherein the signal control circuit is configured to set all of the second data to be one of a logic high and a logic low during a parallel bit test (PBT) operation.

14. A system comprising:
a partial chip; and
a memory controller configured to control an operation of the partial chip,
wherein the partial chip includes:
a memory cell array including a pass region and a fail region; and
a signal control circuit configured to generate second data corresponding to first data to be output from the fail region,
wherein the signal control circuit is configured to bypass third data output from the pass region to a data comparison circuit in the system,
wherein the signal control circuit is configured to set all of the second data to be one of a logic high and a logic low during a parallel bit test (PBT) operation.

15. The system of claim 14 , wherein the memory controller is embodied inside an application processor.

16. The system of claim 14 , wherein the system is a smart phone, a tablet personal computer, or a wearable computer.

17. A partial chip comprising:
a first bank including a pass sub block and a fail sub block;
a signal control circuit configured to generate second data corresponding to first data to be output from the fail sub block during a parallel bit test (PBT) operation, to output the generated second data to a data comparison circuit, and to bypass third data from the pass sub block to the data comparison circuit; and
a data comparison circuit configured to compare the second data with third data, and to output one of the second and third data according to the comparison result to an output driver of the partial chip.

18. The partial chip of claim 17 , further comprising a control logic configured to select the first bank as a bank on which the PBT operation is performed.

19. The partial chip of claim 17 , further comprising a partial chip control circuit configured to set the pass sub block to be a logic high and the fail sub block to be a logic low.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ryu Young Seok
• Kim Myeong O

Classifications

• G11C29/08 Primary

  Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C29/30

  Accessing single arrays · CPC title

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title