Flat shell for an accelerator card

Patent metadata

Field	Value
Publication number	US-11720735-B2
Application number	US-202117408218-A
Country	US
Kind code	B2
Filing date	Aug 20, 2021
Priority date	Aug 20, 2021
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

First claim

What is claimed is:

1. A method, comprising:
reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry;
synthesizing, using the computer hardware, a kernel specifying user circuitry, wherein the kernel is obtained from the one or more computer readable storage media;
linking, using the computer hardware, the synthesized kernel to the flat shell forming a unified circuit design; and
using the computer hardware, placing and routing the unified circuit design to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

2. The method of claim 1 , wherein the computer hardware is configured to prevent user editing of the flat shell.

3. The method of claim 1 , wherein the platform circuitry implements inputs and outputs of the integrated circuit for communicating with circuits external to the integrated circuit.

4. The method of claim 3 , wherein the platform circuitry defines each interface that couples to the kernel.

5. The method of claim 1 , wherein the flat shell is opened within a workspace of an electronic design application as a block design and the kernel is included within the workspace as a block of the block design.

6. The method of claim 1 , wherein the unified circuit design includes the platform circuitry and the user circuitry in a same partition.

7. The method of claim 1 , wherein the placed and routed circuit design comingles at least a portion of the platform circuitry with at least a portion of the user circuitry on the integrated circuit.

8. The method of claim 1 , wherein the placing and routing the unified circuit design operates without constraining the platform circuitry and without constraining the user circuitry to any particular regions on the integrated circuit.

9. A system, comprising:
a processor configured to initiate operations including:
reading a flat shell from one or more computer readable storage media, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry;
synthesizing a kernel specifying user circuitry, wherein the kernel is obtained from the one or more computer readable storage media;
linking the synthesized kernel to the flat shell forming a unified circuit design; and
placing and routing the unified circuit design to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

10. The system of claim 9 , wherein the processor is configured to prevent user editing of the flat shell.

11. The system of claim 9 , wherein the platform circuitry implements inputs and outputs of the integrated circuit for communicating with circuits external to the integrated circuit.

12. The system of claim 9 , wherein the platform circuitry defines each interface that couples to the kernel.

13. The system of claim 9 , wherein the flat shell is opened within a workspace of an electronic design application as a block design and the kernel is included within the workspace as a block of the block design.

14. The system of claim 9 , wherein the unified circuit design includes the platform circuitry and the user circuitry in a same partition.

15. The system of claim 9 , wherein the placed and routed circuit design comingles at least a portion of the platform circuitry with at least a portion of the user circuitry on the integrated circuit.

16. The system of claim 9 , wherein the placing and routing the unified circuit design operates without constraining the platform circuitry and without constraining the user circuitry to any particular regions on the integrated circuit.

17. A computer program product, comprising:
one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media, wherein the program instructions are executable by computer hardware to initiate operations including:
reading a flat shell from the one or more computer readable storage media, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry;
synthesizing a kernel specifying user circuitry, wherein the kernel is obtained from the one or more computer readable storage media;
linking the synthesized kernel to the flat shell forming a unified circuit design; and
placing and routing the unified circuit design to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

18. The computer program product of claim 17 , wherein the computer hardware, in executing the program instructions, is configured to prevent user editing of the flat shell.

19. The computer program product of claim 17 , wherein the platform circuitry:
implements inputs and outputs of the integrated circuit for communicating with circuits external to the integrated circuit; and
defines each interface that couples to the kernel.

20. The computer program product of claim 17 , wherein the placed and routed circuit design comingles at least a portion of the platform circuitry with at least a portion of the user circuitry on the integrated circuit.

Assignees

• Xilinx Inc

Inventors

• Turullols Sebastian
• Corbett Kyle
• Chakraborty Sudipto
• Pyla Siva Santosh Kumar
• Sharma Ravinder
• Manji Kaustuv
• Pvss Jayaram
• Rozum Stephen P
• Krishna Ch Vamshi
• Puthana Susheel

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/3953

  detailed · CPC title

• G06F30/331 Primary

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title