Amplifier and voltage generation circuit including the same

Patent metadata

Field	Value
Publication number	US-11720127-B2
Application number	US-202017077631-A
Country	US
Kind code	B2
Filing date	Oct 22, 2020
Priority date	Jul 17, 2020
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

A voltage generation circuit includes an amplifier configured to detect a difference between a reference voltage and a feedback voltage according to a control signal and a bias current, and configured to generate a driving signal. The voltage generation circuit also includes a driver configured to generate an internal voltage by driving an external voltage according to the driving signal. The amount of the bias current may be forcibly adjusted by the control signal.

First claim

What is claimed is:

1. An amplifier comprising:
a first stage configured to receive a bias voltage and a control signal independent of the bias voltage, configured to detect and output a difference between a reference voltage and a feedback voltage according to the control signal and a bias current,
wherein the control signal is increased from a first level until an external voltage becomes equal to or more than a set level and the control signal transits to a second level when the external voltage becomes equal to or more than the set level, and
wherein an amount of the bias current is maintained according to the bias voltage until the control signal has the second level, and the amount of the bias current is forcibly increased when the control signal has the second level.

2. The amplifier according to claim 1 , wherein the control signal increases during a power-up process of a semiconductor apparatus.

3. The amplifier according to claim 1 , wherein the first stage comprises:
a first transistor array to which an external voltage is applied in common and having a gate terminal to which a bias voltage is applied in common;
a second transistor array electrically connected to the first transistor array and having a gate terminal to which the control signal is inputted in common;
a third transistor electrically connected to the first transistor array and the second transistor array and configured to receive the reference voltage;
a fourth transistor electrically connected between the third transistor and a ground voltage terminal;
a fifth transistor electrically connected to the first transistor array and the second transistor array and configured to receive the feedback voltage; and
a sixth transistor electrically connected between the fifth transistor and a ground voltage terminal.

4. The amplifier according to claim 3 , wherein the first transistor array includes a plurality of transistors of which all but one are respectively and electrically connected to a plurality of transistors of the second transistor array.

5. The amplifier according to claim 3 , wherein the third transistor is electrically connected in common to one of a plurality of transistors of the first transistor array and the plurality of transistors of the second transistor array.

6. The amplifier according to claim 3 , wherein a plurality of transistors of the first transistor array and a plurality of transistors of the second transistor array are configured to have narrower gate widths than the third, fourth, fifth, and sixth transistors.

7. The amplifier according to claim 3 , wherein the first stage is configured so that a sum of current driving forces of the first transistor array and the second transistor array is substantially equal to a current driving force of each of the third, fourth, fifth, and sixth transistors.

8. The amplifier according to claim 1 , wherein the amount of the bias current is forcibly adjusted by the control signal within a maximum value determined according to the bias voltage.

9. A voltage generation circuit comprising:
an amplifier configured to be input a bias voltage and a control signal independent of the bias voltage, configured to detect a difference between a reference voltage and a feedback voltage according to the control signal and a bias current, and configured to generate a driving signal; and
a driver configured to generate an internal voltage by driving an external voltage according to the driving signal,
wherein the control signal is increased from a first level until the external voltage becomes equal to or more than a set level and the control signal transits to a second level when the external voltage becomes equal to or more than the set level, and
wherein an amount of the bias current is maintained according to the bias voltage until the control signal has the second level, and the amount of the bias current is forcibly increased when the control signal has the second level.

10. The voltage generation circuit according to claim 9 , wherein the control signal increases during a power-up process of a semiconductor apparatus.

11. The voltage generation circuit according to claim 9 , further comprising:
a distribution resistor configured to generate the feedback voltage by distributing the internal voltage; and
a capacitor electrically connected, in parallel with the distribution resistor, between a terminal through which the internal voltage is outputted and a ground voltage terminal.

12. The voltage generation circuit according to claim 9 , wherein the amplifier comprises:
a comparator configured to detect and output the difference between the reference voltage and the feedback voltage according to the bias current; and
a current mirror configured to generate the driving signal according to the output of the comparator.

13. The voltage generation circuit according to claim 12 , wherein the comparator comprises:
a first transistor array to which the external voltage is applied in common and having a gate terminal to which a bias voltage is applied in common;
a second transistor array electrically connected to the first transistor array and having a gate terminal to which the control signal is inputted in common;
a third transistor electrically connected to the first transistor array and the second transistor array and configured to receive the reference voltage;
a fourth transistor electrically connected between the third transistor and a ground voltage terminal;
a fifth transistor electrically connected to the first transistor array and the second transistor array and configured to receive the feedback voltage; and
a sixth transistor electrically connected between the fifth transistor and the ground voltage terminal.

14. The voltage generation circuit according to claim 13 , wherein the first transistor array includes a plurality of transistors of which all but one are respectively and electrically connected to a plurality of transistors of the second transistor array.

15. The voltage generation circuit according to claim 13 , wherein the third transistor is electrically connected in common to one of a plurality of transistors of the first transistor array and a plurality of transistors of the second transistor array.

16. The voltage generation circuit according to claim 13 , wherein a plurality of transistors of the first transistor array and a plurality of transistors of the second transistor array are configured to have narrower gate widths than the third, fourth, fifth, and sixth transistors.

17. The voltage generation circuit according to claim 13 , wherein the comparator is configured so that a sum of current driving forces of the first transistor array and the second transistor array is substantially equal to a current driving force of each of the third, fourth, fifth, and sixth transistors.

18. The voltage generation circuit according to claim 12 , wherein the current mirror comprises:
a first transistor configured to receive the external voltage;
a second transistor electrically connected between the first transistor and a ground voltage terminal;
a third transistor configured to receive the external voltage and having a gate terminal electrically connected to the first transistor; and
a fourth transistor electrically connected between the third transistor and the ground voltage terminal,
wherein the driving signal is generated at a node to which the third transistor and the fourth transistor are electrically connected.

19. The voltage generation circuit according to claim 9 , wh

Assignees

• Sk Hynix Inc

Inventors

• Choi Suk Hwan

Classifications

• G05F1/461 Primary

  using an operational amplifier as final control device · CPC title

• G05F1/445

  being transistors in series with the load · CPC title

• G05F1/575 Primary

  characterised by the feedback circuit · CPC title

• H03F3/45 Primary

  Differential amplifiers (differential sense amplifiers G11C7/062) · CPC title

• H03F3/45192 Primary

  Folded cascode stages · CPC title