Array substrate, dimming liquid crystal panel, and display panel

Patent metadata

Field	Value
Publication number	US-11719979-B2
Application number	US-201916977938-A
Country	US
Kind code	B2
Filing date	Nov 28, 2019
Priority date	Nov 28, 2019
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

The present disclosure provides an array substrate, a dimming liquid crystal panel and a display panel. The array substrate includes: a first transparent electrode layer with a plurality of slit structures, wherein the first transparent electrode layer comprises a plurality of domains, the plurality of domains comprise at least two types of domains, each of the plurality of domains is adjacent to different types of domains along both a row direction and a column direction; and a plurality of gate lines extending along the row direction and a plurality of data lines extending along the column direction, the plurality of gate lines and the plurality of data lines crossing to define a plurality of dimming regions arranged in an array.

First claim

What is claimed is:

1. An array substrate comprising:
a first transparent electrode layer with a plurality of slit structures, wherein the first transparent electrode layer comprises a plurality of domains, the plurality of domains comprise at least two types of domains, each of the plurality of domains is adjacent to different types of domains along both a row direction and a column direction, slit structures located in a same type of domain extend in a same direction, and slit structures located in different types of domains extend in different directions; and
a plurality of gate lines extending along the row direction and a plurality of data lines extending along the column direction, the plurality of gate lines and the plurality of data lines crossing to define a plurality of dimming regions arranged in an array, wherein each of the plurality of dimming regions is overlapped with the at least two types of domains in the first transparent electrode layer,
wherein:
each of the plurality of gate lines extends in a fold-line waveform along the row direction, and comprises a plurality of first fold line units arranged periodically, wherein each of the plurality of first fold line units comprises two first straight line segments symmetrically arranged with the column direction as a symmetry axis;
each of the plurality of data lines extends in a fold-line waveform along the column direction and comprises a plurality of second fold line units arranged periodically, wherein each of the plurality of second fold line units comprises a first subsegment and a second subsegment which are centrosymmetric, and the first subsegment and the second subsegment each comprise two second straight line segments symmetrically arranged with the row direction as a symmetric axis; and
the array substrate further comprises: a common electrode line located between adjacent two of the plurality of data lines, wherein the common electrode line extends in a fold-line waveform along the column direction and comprises a plurality of third fold line units arranged periodically, each of the plurality of third fold line units comprises a third subsegment and a fourth subsegment which are centrosymmetric, and the third subsegment and the fourth subsegment each comprise two third straight line segments symmetrically arranged with the row direction as a symmetric axis.

2. The array substrate according to claim 1 , wherein a ratio of an area of one of the plurality of domains to an area of one of the plurality of dimming regions is equal to or greater than 1/16 and equal to or less than ½.

3. The array substrate according to claim 1 , wherein shapes of the common electrode line and one of the plurality of data lines are substantially symmetrical with respect to the column direction, or the shapes of the common electrode line and one of the plurality of data lines are substantially the same.

4. The array substrate according to claim 1 , wherein in a direction perpendicular to the array substrate, an end point of each of the plurality of first fold line units coincides with an end point or a midpoint of one of the plurality of second fold line units, and a midpoint of each of the plurality of first fold line units coincides with an end point or a midpoint of one of the plurality of third fold line units.

5. The array substrate according to claim 4 , wherein in the direction perpendicular to the array substrate, second straight line segments and third straight line segments located in the same type of domain extend in the same direction as slit structures extend.

6. The array substrate according to claim 5 , wherein an acute angle formed by one of the plurality of slit structures and the column direction is in a range greater than or equal to 7 degrees, and less than or equal to 11 degrees.

7. The array substrate according to claim 1 , wherein the plurality of domains are rectangular in shape and same in size, and the plurality of domains comprises two types of domains arranged in a mosaic shape.

8. The array substrate according to claim 7 , wherein:
in a direction perpendicular to the array substrate, each of the first straight line segments substantially coincides with one of diagonal lines of a rectangle comprising two adjacent domains along the row direction and two adjacent domains along the column direction; and
an orthographic projection of one of the plurality of second fold line units and one of the plurality of third fold line units in the column direction is substantially equal to four times a length of a long side of one of the plurality of domains.

9. The array substrate according to claim 1 , wherein the shape of each of the plurality of domains comprises triangle, rectangle, diamond, trapezoid, or polygon with a number of sides greater than four.

10. The array substrate according to claim 1 , wherein the plurality of domains comprise two types of domains, one type of domains comprises a trapezoidal first domain and a triangular second domain, and the other type of domains comprises a trapezoidal third domain and a triangular fourth domain, wherein:
the trapezoidal first domain and the triangular fourth domain are adjacent in the column direction and are spliced into a first isosceles triangle, and in a direction perpendicular to the array substrate, two sides of the first isosceles triangle substantially coincide with one of the plurality of first fold line units; and
the triangular second domain and the trapezoidal third domain are adjacent in the column direction and are spliced into a second isosceles triangle, and in the direction perpendicular to the array substrate, two sides of the second isosceles triangle substantially coincide with one of the plurality of first fold line units.

11. The array substrate according to claim 10 , wherein:
an area ratio of the trapezoidal first domain to the triangular fourth domain is 3:1, and an area ratio of the trapezoidal third domain to the triangular second domain is 3:1; and
an orthographic projection of one of the plurality of second fold line units and one of the plurality of third fold line units in the column direction is substantially equal to four times a height of the trapezoidal first domain.

12. The array substrate according to claim 1 , further comprising thin film transistors disposed at crossings of gate lines and data lines and connected to the gate lines and the data lines, wherein:
the thin film transistors arranged along the row direction are arranged on a same side of the data lines adjacent to the thin film transistors; and
the thin film transistors arranged along the column direction are alternately arranged on both sides of each of the data lines adjacent to the thin film transistors.

13. The array substrate according to claim 12 , further comprising a second transparent electrode layer insulated and spaced apart from the first transparent electrode layer, wherein the second transparent electrode layer is configured to form a fringe electric field with the first transparent electrode layer to control deflection of liquid crystal molecules.

14. A dimming liquid crystal panel comprising: an array substrate according to claim 1 , an opposite substrate spaced apart from the array substrate, and a liquid crystal layer located between the array substrate and the opposite substrate.

15. A display panel comprising: the dimming liquid crystal panel according to claim 14 , and a display liquid crystal panel located on a light emission side of the dimming liquid crystal panel.

16. The dimming liquid crystal panel according to claim 14 , wherein a ratio of an area o

Assignees

• Hefei Boe Display Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Du Yue
• Guo Wei
• Dai Ke
• Guo Lei
• Jiang Liangliang
• Liu Jiaqing
• Guo Yuanhui

Classifications

• G02F1/133707 Primary

  Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/134336

  Matrix · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/133601 Primary

  for spatial active dimming · CPC title