Array substrate, dimming liquid crystal panel, and display panel

Patent metadata

Field	Value
Publication number	US-2022137470-A1
Application number	US-201916975264-A
Country	US
Kind code	A1
Filing date	Nov 28, 2019
Priority date	Nov 28, 2019
Publication date	May 5, 2022
Grant date	—

Abstract

The present disclosure provides an array substrate, a dimming liquid crystal panel and a display panel. The array substrate includes: a first transparent electrode layer with a plurality of slit structures, wherein the first transparent electrode layer includes a plurality of domains with an equal area, the plurality of domains include at least two types of domains, the at least two types of domains are arranged in a mosaic shape; a plurality of gate lines extending along a row direction and a plurality of data lines extending along a column direction, the plurality of gate lines and the plurality of data lines crossing to define a plurality of dimming regions arranged in an array.

First claim

1 . An array substrate comprising:
a first transparent electrode layer with a plurality of slit structures, wherein the first transparent electrode layer comprises a plurality of domains with an equal area, the plurality of domains comprise at least two types of domains arranged in a mosaic shape, slit structures located in a same type of domain extend in a same direction, and slit structures located in different types of domains extend in different directions; and a plurality of gate lines extending along a row direction and a plurality of data lines extending along a column direction, the plurality of gate lines and the plurality of data lines crossing to define a plurality of dimming regions arranged in an array, wherein each of the dimming regions is overlapped with the at least two types of the domains in the first transparent electrode layer.

2 . The array substrate according to claim 1 , wherein a ratio of an area of one of the plurality of domains to an area of one of the plurality of dimming regions is equal to or greater than 1/16 and equal to or less than ½.

3 . The array substrate according to claim 1 , wherein:
each of the plurality of gate lines extends in a fold-line waveform along the row direction, and comprises a plurality of first fold line units arranged periodically, wherein each of the plurality of first fold line units comprises two first straight line segments symmetrically arranged with the column direction as a symmetry axis; each of the plurality of data lines extends in a fold-line waveform along the column direction and comprises a plurality of second fold line units arranged periodically, wherein each of the plurality of second fold line units comprises a first subsegment and a second subsegment which are centrosymmetric, and the first subsegment and the second subsegment each comprise two second straight line segments symmetrically arranged with the row direction as a symmetric axis; and the array substrate further comprises: a common electrode line located between adjacent two of the plurality of data lines, wherein the common electrode line extends in a fold-line waveform along the column direction and comprises a plurality of third fold line units arranged periodically, each of the plurality of third fold line units comprises a third subsegment and a fourth subsegment which are centrosymmetric, and the third subsegment and the fourth subsegment each comprise two third straight line segments symmetrically arranged with the row direction as a symmetric axis.

4 . The array substrate according to claim 3 , wherein shapes of the common electrode line and one of the plurality of data lines are substantially symmetrical with respect to the column direction, or the shapes of the common electrode line and one of the plurality of data lines are substantially the same.

5 . The array substrate according to claim 3 , wherein in a direction perpendicular to the array substrate, an end point of each of the plurality of first fold line units coincides with an end point or a midpoint of one of the plurality of second fold line units, and a midpoint of each of the plurality of first fold line units coincides with an end point or a midpoint of one of the plurality of third fold line units.

6 . The array substrate according to claim 5 , wherein in the direction perpendicular to the array substrate, second straight line segments and third straight line segments located in the same type of domain extend in the same direction as slit structures extend.

7 . The array substrate according to claim 6 , wherein an acute angle formed by one of the plurality of slits and the column direction is in a range greater than or equal to 7 degrees, and less than or equal to 11 degrees.

8 . The array substrate according to claim 3 , wherein the plurality of domains are the same in shape and size and are isosceles triangles, and each of the plurality of domains comprises two types of domains.

9 . The array substrate according to claim 8 , wherein:
in a direction perpendicular to the array substrate, each of the first straight line segments substantially coincides with a side of two of the isosceles triangles located on the same side; and an orthographic projection of one of the plurality of second fold line units and one of the plurality of third fold line units in the column direction is substantially equal to four times a height of the isosceles triangle.

10 . The array substrate according to claim 1 , wherein the first transparent electrode layer comprises:
a plurality of trunk electrodes, wherein each of the plurality of trunk electrodes is located between two adjacent domains with different types, and at least one of the trunk electrodes extends along the row direction; and a plurality of branch electrodes connected to the trunk electrodes on both sides of each of the trunk electrodes, wherein in one of the domains, branch electrodes and slit structures extend in the same direction, and adjacent two branch electrodes are spaced apart by a slit structure.

11 . The array substrate according to claim 1 , further comprising thin film transistors disposed at crossings of gate lines and data lines and connected to the gate lines and the data lines, wherein:
the thin film transistors arranged along the row direction are arranged on a same side of the data lines adjacent to the thin film transistors; and the thin film transistors arranged along the column direction are alternately arranged on both sides of each of the data lines adjacent to the thin film transistors.

12 . The array substrate according to claim 11 , wherein in a direction perpendicular to the array substrate, the thin film transistors are located in the same type of the domains.

13 . The array substrate according to claim 11 , further comprising a second transparent electrode layer insulated and spaced apart from the first transparent electrode layer, wherein the second transparent electrode layer is configured to form a fringe electric field with the first transparent electrode layer to control deflection of liquid crystal molecules.

14 . A dimming liquid crystal panel comprising: an array substrate according to claim 1 , an opposite substrate spaced apart from the array substrate, and a liquid crystal layer located between the array substrate and the opposite substrate.

15 . A display panel comprising: the dimming liquid crystal panel according to claim 14 , and a display liquid crystal panel located on one side of the dimming liquid crystal panel.

16 . The display panel according to claim 15 , wherein the first transparent electrode layer comprises:
a plurality of trunk electrodes, wherein each of the plurality of trunk electrodes is located between two adjacent domains with different types, at least one of the plurality of trunk electrodes extends along the row direction, a line width of the trunk electrode extending along the row direction is smaller than a line width of a gate line of the display liquid crystal panel, and in a direction perpendicular to the display liquid crystal panel, a trunk electrode extending along the row direction is at least partially overlapped with the gate line of the display liquid crystal panel; and a plurality of branch electrodes connected to trunk electrodes on both sides of each of the trunk electrodes, wherein in one of the domains, branch electrodes and slits extend in the same direction, and adjacent two branch electrodes are spaced apart by a slit structure.

17 . The display panel according to claim 16 , wherein the trunk electrode extending along the row

Assignees

• Hefei Boe Display Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Du Yue
• Zhang Yuntian
• Jiang Liangliang
• Guo Lei
• Dai Ke
• Liu Jiaqing

Classifications

• G02F1/134372

  for fringe field switching [FFS] where the common electrode is not patterned · CPC title

• G02F1/13471

  in which all the liquid crystal cells or layers remain transparent, e.g. FLC, ECB, DAP, HAN, TN, STN, SBE-LC cells (G02F1/13475 takes precedence) · CPC title

• G02F1/133707 Primary

  Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes · CPC title

• G02F1/133601

  for spatial active dimming · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title