Semiconductor wafer testing system and related method for improving external magnetic field wafer testing

Patent metadata

Field	Value
Publication number	US-11719742-B2
Application number	US-202217882827-A
Country	US
Kind code	B2
Filing date	Aug 8, 2022
Priority date	Sep 24, 2018
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.

First claim

What is claimed is:

1. A semiconductor wafer testing system, comprising:
a wafer chuck support structure;
a ferromagnetic wafer chuck disposed on the wafer chuck support structure, wherein the ferromagnetic wafer chuck is configured to hold a semiconductor wafer comprising an integrated chip (IC), wherein the ferromagnetic wafer chuck has a chemical composition from an upper surface of the ferromagnetic wafer chuck to a lower surface of the ferromagnetic wafer chuck, and wherein the chemical composition comprises about 99.9% of a ferromagnetic material; and
a magnet configured to generate an external magnetic field, wherein the ferromagnetic wafer chuck is configured to amplify the external magnetic field so that the external magnetic field passes through the IC with an amplified magnetic field strength.

2. The semiconductor wafer testing system of claim 1 , further comprising:
a wafer probing housing, wherein the wafer chuck support structure is disposed in the wafer probing housing.

3. The semiconductor wafer testing system of claim 2 , further comprising:
a wafer chuck positioning controller configured to provide wafer positioning signals to the wafer chuck support structure, wherein the wafer chuck support structure is configured to position the ferromagnetic wafer chuck at various locations inside the wafer probing housing in response to receiving the wafer positioning signals.

4. The semiconductor wafer testing system of claim 3 , further comprising:
a wafer probing unit comprising the wafer probing housing, wherein the wafer probing unit is configured to receive a wafer carrier and automatically remove the semiconductor wafer from the wafer carrier and place the semiconductor wafer on the ferromagnetic wafer chuck.

5. The semiconductor wafer testing system of claim 4 , wherein the magnet is disposed outside of the wafer probing housing.

6. The semiconductor wafer testing system of claim 1 , wherein the ferromagnetic wafer chuck is configured to hold the semiconductor wafer along the upper surface of the ferromagnetic wafer chuck.

7. The semiconductor wafer testing system of claim 6 , wherein the ferromagnetic wafer chuck directly contacts the wafer chuck support structure.

8. The semiconductor wafer testing system of claim 7 , wherein the lower surface of the ferromagnetic wafer chuck directly contacts an upper surface of the wafer chuck support structure.

9. The semiconductor wafer testing system of claim 1 , wherein the amplified magnetic field strength is greater than a non-amplified maximum magnetic field strength of the magnet, and wherein the non-amplified maximum magnetic field strength of the magnet is less than or equal to about 0.01 tesla (T).

10. A semiconductor wafer testing system, comprising:
an electromagnet;
a power supply electrically coupled to the electromagnet;
a power supply controller electrically coupled to the power supply, wherein the power supply controller is configured to provide a magnetic field strength signal to the power supply, wherein the power supply is configured to provide an electrical current that corresponds to the magnetic field strength signal to the electromagnet, and wherein the electromagnet is configured to generate a magnetic field in response to receiving the electrical current; and
a ferromagnetic wafer chuck configured to hold a semiconductor wafer, wherein the semiconductor wafer comprises a device, and wherein the ferromagnetic wafer chuck is configured to amplify the magnetic field so that the magnetic field passes through the device with an amplified magnetic field strength.

11. The semiconductor wafer testing system of claim 10 , further comprising:
a tester system comprising tester circuitry, wherein the power supply controller is electrically coupled to the tester circuitry, and wherein the tester circuitry is configured to provide a magnetic field test signal that corresponds to the magnetic field strength signal to the power supply controller; and
a wafer prober electrically coupled to the tester circuitry, wherein the wafer prober is configured to electrically couple the device to the tester circuitry via one or more conductive probes, wherein the tester circuitry is configured to perform an electrical test on the device by providing one or more test signals to the device via the one or more conductive probes.

12. The semiconductor wafer testing system of claim 11 , further comprising:
a temperature management controller electrically coupled to the tester circuitry; and
a wafer heating element, wherein the tester system is configured to provide one or more temperature control signals to the wafer heating element via the temperature management controller so that the wafer heating element heats the semiconductor wafer to one or more predefined temperatures.

13. The semiconductor wafer testing system of claim 12 , further comprising:
a wafer chuck support structure, wherein the ferromagnetic wafer chuck is mounted to the wafer chuck support structure;
a wafer chuck positioning controller electrically coupled to the tester circuitry and the wafer chuck support structure; and
the tester system is configured to provide one or more wafer positioning signals to the wafer chuck support structure via the wafer chuck positioning controller so that the wafer chuck support structure positions the ferromagnetic wafer chuck at one or more locations.

14. The semiconductor wafer testing system of claim 13 , wherein:
the semiconductor wafer comprises a plurality of integrated circuits (ICs), wherein a first integrated circuit (IC) of the plurality of ICs comprises the device, and wherein each of the one or more locations corresponds to a position in which one of the plurality of ICs is disposed on the semiconductor wafer.

15. An apparatus, comprising:
a magnet configured to generate an external magnetic field; and
a ferromagnetic wafer chuck having an upper surface and a lower surface, wherein the ferromagnetic wafer chuck is configured to hold a semiconductor wafer along the upper surface, wherein the ferromagnetic wafer chuck is configured to be mounted to a wafer chuck pedestal along the lower surface of the ferromagnetic wafer chuck, wherein the ferromagnetic wafer chuck has a chemical composition from the upper surface to the lower surface, wherein the chemical composition of the ferromagnetic wafer chuck comprises about 99.9% of a ferromagnetic material, and wherein the ferromagnetic wafer chuck is configured to amplify the external magnetic field so that the external magnetic field passes through the semiconductor wafer with an amplified magnetic field strength.

16. The apparatus of claim 15 , wherein:
the upper surface of the ferromagnetic wafer chuck is an uppermost surface of the ferromagnetic wafer chuck; and
the lower surface of the ferromagnetic wafer chuck is a lowermost surface of the ferromagnetic wafer chuck.

17. The apparatus of claim 15 , wherein the ferromagnetic wafer chuck has the chemical composition from a first point on a sidewall of the ferromagnetic wafer chuck to a second point on the sidewall of the ferromagnetic wafer chuck, wherein the second point is opposite the first point, and wherein the sidewall of the ferromagnetic wafer chuck extends laterally in a closed loop path.

18. The apparatus of claim 17 , wherein the ferromagnetic wafer chuck is disc shaped.

19. The apparatus of claim 18 , wherein the ferromagnetic material is either iron, cobalt, or nickel.

20. The apparatus of claim 19 , wherein the ferromagnet

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chuang Harry-Hak-Lay
• Chang Chih-Yang
• Wang Ching-Huang
• Chiang Tien-Wei
• Shih Meng-Chun
• Wang Chia Yu

Classifications

• G01R31/2865 Primary

  Holding devices, e.g. chucks; Handlers or transport devices (having contacts G01R31/2863) · CPC title

• G01R1/16

  Magnets · CPC title

• G01R31/2887

  involving moving the probe head or the IC under test; docking stations (moving single probes G01R1/06705; moving individual probes in multiple probes G01R1/07392) · CPC title

• G01R31/2891

  related to sensing or controlling of force, position, temperature (G01R31/2874 takes precedence; sensing of force G01L; sensing of position G01B, G01D; sensing of temperature G01K; controlling in general G05) · CPC title

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title