Post-CMP cleaning composition for germanium-containing substrate

Patent metadata

Field	Value
Publication number	US-11718812-B2
Application number	US-202117191534-A
Country	US
Kind code	B2
Filing date	Mar 3, 2021
Priority date	May 28, 2020
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

A cleaning composition for cleaning a surface of a substrate comprising silicon germanium after a chemical mechanical polishing process is provided. The cleaning composition includes an oligomeric or polymeric polyamine, at least one wetting agent, a pH adjusting agent, and a solvent.

First claim

What is claimed is:

1. A method for removing contaminants from a substrate after a chemical mechanical polishing process, comprising:
providing the substrate, wherein a surface layer of the substrate compresses a silicon germanium region; and
cleaning the surface layer of the substrate with a cleaning composition, the cleaning composition comprising an oligomeric or polymeric polyamine, wherein cleaning the surface layer of the substrate comprises:
supplying the cleaning composition to the surface layer of the substrate; and
mechanically brushing the surface layer of the substrate while the cleaning composition is supplied to the surface.

2. The method of claim 1 , wherein the oligomeric or polymeric polyamine comprises diethylenediamine, triethylenetetramine, tetraethylenepentamine, polyethyleneimine or polyvinyl amine.

3. The method of claim 1 , wherein the oligomeric or polymeric polyamine comprises one or more hydroxyl functional groups.

4. The method of claim 1 , wherein the oligomeric or polymeric polyamine is a primary amine, a secondary amine, a tertiary amine or a quaternary amine having at least two amino groups.

5. A method of forming a semiconductor structure, comprising:
forming a first fin in a first region of a substrate and a second fin in a second region of the substrate, the first fin comprising a first semiconductor material, the second fin comprising a second semiconductor material different from the first semiconductor material;
performing a chemical mechanical polishing process to reduce a height of the first fin and a height of the second fin; and
cleaning surfaces of the first fin and the second fin using a cleaning composition, the cleaning composition comprising an oligomeric or polymeric polyamine.

6. The method of claim 5 , wherein the first fin comprises silicon, and the second fin comprises SiGe.

7. The method of claim 5 , wherein the oligomeric or polymeric polyamine comprises diethylenediamine, triethylenetetramine, tetraethylenepentamine, polyethyleneimine or polyvinyl amine.

8. The method of claim 5 , wherein the oligomeric or polymeric polyamine comprises one or more hydroxyl functional groups.

9. The method of claim 5 , further comprising cleaning the surfaces of the first fin and the second fin using deionized water.

10. The method of claim 1 , wherein the cleaning composition further comprises a solvent.

11. A method for forming a semiconductor structure, comprising:
forming a plurality of fins extending from a substrate, the plurality of fins separated from one another by isolation structures and comprising a first fin in a first region of the substrate and a second fin in a second region of the substrate;
planarizing top surfaces of the plurality of fins and the isolation structures by a chemical mechanical polishing (CMP) process;
removing contaminants generated by the CMP process from the top surfaces of the plurality of fins and the isolation structures by applying a cleaning composition to the top surfaces of the plurality of fins and the isolation structures, wherein the cleaning composition comprises an oligomeric or polymeric polyamine, at least one wetting agent, a pH adjusting agent and a solvent; and
recessing the isolation structures to expose upper portions of the plurality of fins.

12. The method of claim 11 , wherein the oligomeric or polymeric polyamine comprises diethylenediamine, triethylenetetramine, tetraethylenepentamine, polyethyleneimine or polyvinyl amine.

13. The method of claim 11 , wherein the at least one wetting agent comprises an anionic, cationic, non-ionic or zwitterionic surfactant.

14. The method of claim 11 , wherein the pH adjusting agent comprises an organic acid selected from C1-C6 alkyl carboxylic acid, nitric acid, sulfuric acid and C1-C6 alkyl sulfonic acid.

15. The method of claim 11 , wherein the first fin comprises silicon, and the second fin comprises a Ge-containing semiconductor material.

16. The method of claim 11 , wherein removing the contaminants generated by the CMP process from the top surfaces of the plurality of fins and the isolation structures comprises:
rotating the substrate as the cleaning composition is applied to the top surfaces of the plurality of fins and the isolation structures; and
brushing the top surfaces of the plurality of fins and the isolation structures using a brush.

17. The method of claim 16 , wherein removing the contaminants generated by the CMP process from the top surfaces of the plurality of fins and the isolation structures further comprises rinsing the top surfaces of the plurality of fins and the isolation structures with water.

18. The method of claim 11 , wherein the top surfaces of the plurality of fins have a surface roughness less than 20 nm after cleaning with the cleaning composition.

19. The method of claim 11 , further comprising:
patterning the substrate to form a plurality of semiconductor fins in the first region and the second region of the substrate;
removing a semiconductor fin of the plurality of semiconductor fins from the second region of the substrate; and
depositing a semiconductor material to epitaxially grow the second fin in the second region of the substate, thereby forming the plurality of fins.

20. The method of claim 11 , wherein the isolation structures comprise silicon oxide, silicon nitride or silicon oxynitride.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cui Ji
• Hong William Weilun
• Huang Gin-Chen
• Suen Shich-Chang
• Chen Kei-Wei

Classifications

• H10P70/00

  Cleaning of wafers, substrates or parts of devices · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P72/0414

  using mainly spraying means, e.g. nozzles · CPC title