Method to etch non-volatile metal materials
US-2015340603-A1 · Nov 26, 2015 · US
Method for manufacturing a magnetic semiconductor memory MRAM comprising etching a magnetic tunnel junction layer formed on a lower electrode utilizing an upper electrode having annular shape
US9196826B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9196826-B2 |
| Application number | US-201414536322-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 7, 2014 |
| Priority date | Mar 24, 2011 |
| Publication date | Nov 24, 2015 |
| Grant date | Nov 24, 2015 |
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Abstract
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A method for manufacturing a semiconductor memory device includes forming a magnetic tunnel junction layer on a lower electrode, forming a spacer having an annular shape on the magnetic tunnel junction layer, forming upper electrodes on both sidewall surfaces of the annular shaped spacer, removing the spacer, and etching the magnetic tunnel junction layer by using the upper electrodes as an etch mask.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for manufacturing a semiconductor memory device, comprising: forming a magnetic tunnel junction layer on a lower electrode; forming a spacer having an annular shape on the magnetic tunnel junction layer; forming upper electrodes on both sidewall surfaces of the annular shaped spacer; removing the spacer; and etching the magnetic tunnel junction layer by using the upper electrodes as an etch mask. 2. The method as recite…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Physics · mapped topic
- H01L43/12Primary
Electricity · mapped topic
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- What does patent US9196826B2 cover?
- A method for manufacturing a semiconductor memory device includes forming a magnetic tunnel junction layer on a lower electrode, forming a spacer having an annular shape on the magnetic tunnel junction layer, forming upper electrodes on both sidewall surfaces of the annular shaped spacer, removing the spacer, and etching the magnetic tunnel junction layer by using the upper electrodes as an etc…
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H01L43/12. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).