Barrier structure configured to increase performance of III-V devices

Patent metadata

Field	Value
Publication number	US-11715792-B2
Application number	US-202016872551-A
Country	US
Kind code	B2
Filing date	May 12, 2020
Priority date	Jan 31, 2020
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

First claim

What is claimed is:

1. A method of forming an integrated chip, comprising:
depositing an undoped layer over a substrate;
depositing a first barrier layer over the undoped layer, wherein the first barrier layer comprises a ternary III-V semiconductor material with a first atomic percentage of a first element;
forming a doped layer over the first barrier layer;
selectively forming a second barrier layer over the first barrier layer such that the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance, wherein the second barrier layer comprises the ternary III-V semiconductor material with a second atomic percentage of the first element, wherein the second atomic percentage is greater than the first atomic percentage; and
forming a gate electrode over the doped layer.

2. The method of claim 1 , wherein selectively forming the second barrier layer comprises:
forming a masking layer over the doped layer and the first barrier layer; and
performing a selective growth process to form the second barrier layer over the first barrier layer in regions laterally offset from the masking layer.

3. The method of claim 2 , wherein the first barrier layer is deposited by an epitaxial process and the selective growth process includes performing a metal organic chemical vapor deposition (MO-CVD) process.

4. The method of claim 1 , further comprising:
forming a first contact and a second contact on the second barrier layer and laterally spaced apart from one another by the doped layer.

5. The method of claim 1 , wherein the ternary III-V semiconductor material is aluminum gallium nitride.

6. The method of claim 1 , wherein a bottom surface of the second barrier layer is disposed below a top surface of the first barrier layer.

7. The method of claim 1 , wherein the first barrier layer has a first thickness within a middle region of the substrate, wherein the second barrier layer comprises a second thickness and is laterally offset from the middle region, wherein the first barrier layer has a third thickness within a peripheral region that is laterally offset from the middle region, and wherein the first thickness is greater than the second thickness and the third thickness.

8. The method of claim 7 , wherein the third thickness is greater than the second thickness.

9. The method of claim 1 , wherein the second barrier layer is selectively formed at a temperature within a range of about 700 to 1200 degrees Celsius.

10. A method of forming an integrated chip, comprising:
depositing an undoped layer over a substrate;
depositing a first barrier layer on the undoped layer, wherein the first barrier layer comprises a ternary III-V semiconductor material;
forming a doped layer on the first barrier layer;
forming a masking layer on the doped layer and laterally within a middle region of the first barrier layer;
selectively forming a second barrier layer directly contacting the first barrier layer with the masking layer in place, wherein the second barrier layer comprises the ternary III-V semiconductor material, wherein the second barrier layer abuts sidewalls of the masking layer;
removing the masking layer;
forming a gate electrode over the doped layer; and
forming a first contact and a second contact on the second barrier layer and spaced laterally apart from one another by the gate electrode.

11. The method of claim 10 , wherein the first barrier layer has a first atomic percentage of a first element and the second barrier layer has a second atomic percentage of the first element, wherein the second atomic percentage is different from the first atomic percentage.

12. The method of claim 11 , wherein the first element is aluminum, the first atomic percentage is within a range of about 7 to 25 percent and the second atomic percentage is within a range of about 10 to 60 percent.

13. The method of claim 11 , wherein the first barrier layer has a first thickness and the second barrier layer has a second thickness less than the first thickness.

14. The method of claim 13 , wherein the first thickness is within a range of about 8 to 25 nanometers and the second thickness is within a range of about 1 to 10 nanometers.

15. The method of claim 10 , wherein the second barrier layer is selectively formed by a metal organic chemical vapor deposition (MO-CVD) process at a temperature within a range of about 700 to 1200 degrees Celsius.

16. The method of claim 10 , further comprising:
forming a lower buffer layer between the undoped layer and the substrate.

17. A method of forming an integrated chip, comprising:
depositing an undoped layer over a substrate;
depositing a first barrier layer on the undoped layer by a first deposition process;
forming a doped layer directly on the first barrier layer, wherein the doped layer is spaced within a middle region of the substrate; and
depositing a second barrier layer directly on the first barrier layer by a second deposition process different from the first deposition process, wherein the second barrier layer is deposited in a peripheral region laterally offset from the doped layer, wherein the first and second barrier layers comprise a III-V semiconductor material with a first element, wherein a first atomic concentration of the first element in the middle region is less than a second atomic concentration of the first element in the peripheral region, and wherein at least a portion of the first barrier layer decomposes and/or is removed in the peripheral region during the second deposition process.

18. The method of claim 17 , wherein the second barrier layer has a first thickness in the middle region and a second thickness in the peripheral region, wherein the first thickness is greater than the second thickness.

19. The method of claim 17 , wherein a top surface of the second barrier layer is vertically below a top surface of the doped layer.

20. The method of claim 17 , further comprising:
forming a passivation layer over the second barrier layer, wherein the passivation layer continuously extends from a top surface of the second barrier layer, along a sidewall of the second barrier layer, to a top surface of the first barrier layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Yun-Hsiang
• Tsai Chun Lin
• Yu Jiun-Lei Jerry
• Chen Po-Chih
• Yeh Chia-Ling
• Chen Ching Yu

Classifications

• H10D30/4755

  having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H10D30/015

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title

• H10D62/343

  Gate regions of field-effect devices having PN junction gates · CPC title