Display device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11715739-B2
Application number	US-202117338738-A
Country	US
Kind code	B2
Filing date	Jun 4, 2021
Priority date	Sep 8, 2020
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

An embodiment provides a manufacturing method of a polycrystalline silicon layer, including: forming a first amorphous silicon layer on a substrate; doping an N-type impurity into the first amorphous silicon layer; forming a second amorphous silicon layer on the n-doped first amorphous silicon layer; doping a P-type impurity into the second amorphous silicon layer; and crystalizing the n-doped first amorphous silicon layer and the p-doped second amorphous silicon layer by irradiating a laser beam onto n-doped first amorphous silicon layer and the p-doped second amorphous silicon layer to form a polycrystalline silicon layer.

First claim

What is claimed is:

1. A manufacturing method of a polycrystalline silicon layer, the method comprising:
forming a first amorphous silicon layer on a substrate;
doping an N-type impurity into the first amorphous silicon layer to form an n-doped first amorphous silicon layer;
forming a second amorphous silicon layer on the n-doped first amorphous silicon layer;
doping a P-type impurity into the second amorphous silicon layer to form a p-doped second amorphous silicon layer; and
crystalizing the n-doped first amorphous silicon layer and the p-doped second amorphous silicon layer by irradiating a laser beam onto the n-doped first amorphous silicon layer and the p-doped second amorphous silicon layer to form a polycrystalline silicon layer.

2. The manufacturing method of claim 1 , further comprising cleaning the substrate on which the n-doped first amorphous silicon layer and the p-doped second amorphous silicon layer is disposed before the crystalizing the n-doped first amorphous silicon layer and the p-doped second amorphous silicon layer,
wherein the cleaning of the substrate includes:
cleaning the substrate with hydrofluoric acid; and
rinsing the substrate with deionized water.

3. The manufacturing method of claim 2 , wherein a contact angle with respect to water measured on a surface of the p-doped second amorphous silicon layer is less than 20 degrees after the cleaning of the p-doped second amorphous silicon layer with hydrofluoric acid.

4. The manufacturing method of claim 1 , wherein a thickness of the first amorphous silicon layer is 150 Å or more and 250 Å or less.

5. The manufacturing method of claim 1 , wherein a thickness of the second amorphous silicon layer is 150 Å or more and 250 Å or less.

6. The manufacturing method of claim 1 , wherein the doping of the N-type impurity proceeds with an acceleration voltage of more than 0 and 20 keV or less and a dose of 1e14 atoms/cm2 or more and 1e16 atoms/cm2 or less.

7. The manufacturing method of claim 1 , wherein the doping of the P-type impurity proceeds with an acceleration voltage of more than 0 and 20 keV or less and a dose of 1e14 atoms/cm2 or more and 1e16 atoms/cm2 or less.

8. A display device comprising:
a substrate;
a thin film transistor disposed on the substrate; and
a display element disposed on the thin film transistor,
wherein the thin film transistor includes:
an active pattern disposed on the substrate, the active pattern including a source region, a drain region, and a channel region disposed between the source region and the drain region;
a gate insulating layer disposed on the active pattern; and
a gate electrode disposed on the gate insulating layer in a region corresponding to the channel region,
wherein the channel region includes an N-type impurity and a P-type impurity, and
wherein concentration of the P-type impurity increases as the channel region approaches the gate insulating layer.

9. The display device of claim 8 , wherein concentration of the N-type impurity increases as a distance from the gate insulating layer increases.

10. The display device of claim 8 , wherein the P-type impurity is any one of boron (B) and fluorine (F).

11. The display device of claim 8 , wherein the N-type impurity is phosphorus (P).

12. The display device of claim 8 , wherein a thickness of the active pattern is 300 Å or more and 500 Å or less.

13. The display device of claim 8 ,
wherein concentration of the P-type impurity in the channel region is 1e14 atoms/cm2 or more and 1e16 atoms/cm2 or less.

14. The display device of claim 8 ,
wherein concentration of the N-type impurity in the channel region is 1e14 atoms/cm2 or more and 1e16 atoms/cm2 or less.

15. The display device of claim 8 , wherein concentration of the P-type impurity and concentration of the N-type impurity within the channel region are substantially the same.

16. The display device of claim 8 ,
wherein the thin film transistor further includes a source electrode and a drain electrode that are electrically connected to the source region and the drain region, respectively.

17. The display device of claim 8 , wherein the display element includes:
a first electrode electrically connected to the thin film transistor;
an emission layer disposed on the first electrode; and
a second electrode disposed on the emission layer.

18. A manufacturing method of a display device, the method comprising:
forming a first amorphous silicon layer on a substrate;
doping an N-type impurity into the first amorphous silicon layer to form an n-doped first amorphous silicon layer;
forming a second amorphous silicon layer on the first amorphous silicon layer;
doping a P-type impurity into the second amorphous silicon layer to form a p-doped second amorphous silicon layer;
crystalizing the n-doped first amorphous silicon layer and the p-doped second amorphous silicon layer by irradiating a laser beam onto the n-doped first amorphous silicon layer and the p-doped second amorphous to form a polycrystalline silicon layer;
forming a polycrystalline silicon pattern by patterning the polycrystalline silicon layer;
forming a gate insulating layer on the polycrystalline silicon pattern;
forming a gate electrode on the gate insulating layer;
forming a source region, a drain region, and a channel region between the source region and the drain region by doping the polycrystalline silicon pattern;
forming a display element on the gate electrode.

19. The manufacturing method of claim 18 , further comprising cleaning the substrate on which the n-doped first amorphous silicon layer and the p-doped second amorphous silicon layer is disposed before the crystalizing the n-doped first amorphous silicon layer and the p-doped second amorphous silicon layer,
wherein the cleaning of the substrate includes:
cleaning the substrate with hydrofluoric acid; and rinsing the substrate with deionized water.

20. The manufacturing method of claim 18 , wherein the doping of the N-type impurity proceeds with an acceleration voltage of more than 0 and 20 keV or less and a dose of 1e14 atoms/cm2 or more and 1e16 atoms/cm2 or less.

21. The manufacturing method of claim 18 , wherein the doping of the P-type impurity proceeds with an acceleration voltage of more than 0 and 20 keV or less and a dose of 1e14 atoms/cm2 or more and 1e16 atoms/cm2 or less.

22. The manufacturing method of claim 18 , further comprising cleaning the substrate on which the n-doped first amorphous silicon layer and the p-doped second amorphous silicon layer is disposed before the crystalizing the n-doped first amorphous silicon layer and the p-doped second amorphous silicon layer,
wherein a contact angle with respect to water measured on a surface of the p-doped second amorphous silicon layer is less than 20 degrees after the cleaning of the p-doped second amorphous silicon layer with hydrofluoric acid.

23. The manufacturing method of claim 18 , wherein the forming the source region, the drain region, and the channel region between the source region and the drain region by doping the polycrystalline silicon pattern is performed by an ion implantation using the gate electrode as a mask.

24. The manufacturing method of claim 18 , further comprising:
forming a source electrode and a drain electrode, the source electrode and the drain electrode being electrically connected to the source region and the drain region, respectively.

25.

Assignees

• Samsung Display Co Ltd

Inventors

• Seo Jong Oh
• Baek Jong Jun

Classifications

• H10P70/27 Primary

  during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers · CPC title

• H10P32/302

  Doping polycrystalline silicon or amorphous silicon layers · CPC title

• H10P14/3808

  using laser beams · CPC title

• H10P14/3411 Primary

  Silicon, silicon germanium or germanium · CPC title

• H10P14/36

  characterised by treatments done before the formation of the materials · CPC title