Monotonic counter

Patent metadata

Field	Value
Publication number	US-11715506-B2
Application number	US-202217691870-A
Country	US
Kind code	B2
Filing date	Mar 10, 2022
Priority date	Mar 15, 2021
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

A monotonic counter stores N binary words representing a value in N memory cells. When i memory cells of consecutive ranks between k modulo N and k+i modulo N each represent a value complementary to a null value, the counter is incremented by erasing a value of a memory cell of rank k+i+1 modulo N. When i+1 memory cells of consecutive ranks between k+1 modulo N and k+i+1 modulo N each represent the value complementary to the null value, the counter is incremented by incrementing a value of a memory cell of rank k modulo N by two step sizes and storing a result in a memory cell of rank k+1 modulo N, wherein, N is an integer greater than or equal to five, k is an integer, and i is an integer between 2 and N−3.

First claim

The invention claimed is:

1. A device comprising:
a non-volatile memory, which, in operation, stores a number N of binary words in N memory cells of the non-volatile memory, the N binary words representing a value of a monotonic counter, each binary word having a size sufficient to store a maximum value of the monotonic counter; and
control circuitry coupled to the memory, wherein the control circuitry, in operation, increments the value of the monotonic counter by a step size, the incrementing the value of the monotonic counter by the step size including:
in response to i memory cells of the N memory cells of consecutive ranks between k modulo N and k+i modulo N each representing a value complementary to a null value, erasing a value of a memory cell of the N memory cells of rank k+i+1 modulo N; and
in response to i+1 memory cells of the N memory cells of consecutive ranks between k+1 modulo N and k+i+1 modulo N each representing the value complementary to the null value, incrementing a value of a memory cell of the N memory cells of rank k modulo N by two step sizes and storing a result of the incrementing of the value of the memory cell of rank k modulo N by two step sizes in a memory cell of the N memory cells of rank k+1 modulo N, wherein,

N is an integer greater than or equal to five,
k is an integer, and
i is an integer between 2 and N−3.

2. The device of claim 1 , wherein the value complementary to the null value is a value of a memory cell of the N memory cells after the memory cell is erased.

3. The device of claim 1 , wherein the memory cells of ranks lower than k−1 modulo N and of ranks higher than k+i+1 modulo N all represent values different from the value complementary to the null value.

4. The device of claim 1 , wherein the monotonic counter represents the null value when a memory cell of the N memory cells representing the null value is followed in rank by i memory cells representing the value complementary to the null value.

5. The device of claim 1 , wherein i is two.

6. The device of claim 5 , wherein the control circuitry, in operation, performs an initialization operation, wherein in response to memory cells of the N memory cells of consecutive ranks between k modulo N and k+2 modulo N representing the value complementary to the null value, the initialization operation includes:
writing the null value in the memory cell of rank k+2 modulo N;
erasing the memory cell of rank k+3 modulo N;
writing any value different from the value complementary to the null value, in the memory cell of rank k+1 modulo N; and
erasing the memory cell of rank k+4 modulo N.

7. The device of claim 6 , herein the writing any value different from the value complementary to the null value, in the memory cell of rank k+1 modulo N, comprises writing the zero value in the memory cell of rank K+1 modulo N.

8. The device of claim 6 , wherein in response to memory cells of the N memory cells of consecutive ranks between k+1 modulo N and k+3 modulo N represent the value complementary to the null value, the initialization operation includes:
writing the null value in the memory cell of rank k+2 modulo N;
writing any value different from the value complementary to the null value in the memory cell of rank k+1 modulo N; and
erasing the value of the memory cell of rank k+4 modulo N.

9. The device according to claim 8 , wherein the writing any value different from the value complementary to the null value, in the memory cell of rank k+1 modulo N, comprises writing the zero value in the memory cell of rank K+1 modulo N.

10. A method, comprising:
storing a number N of binary words in N memory cells of a non-volatile memory, the N binary words representing a value of a monotonic counter, each binary word having a size sufficient to store a maximum value of the monotonic counter; and
incrementing the value of the monotonic counter by a step size, the incrementing the value of the monotonic counter by the step size including:
in response to i memory cells of the N memory cells of consecutive ranks between k modulo N and k+i modulo N each representing a value complementary to a null value, erasing a value of a memory cell of the N memory cells of rank k+i+1 modulo N; and
in response to i+1 memory cells of the N memory cells of consecutive ranks between k+1 modulo N and k+i+1 modulo N each representing the value complementary to the null value, incrementing a value of a memory cell of the N memory cells of rank k modulo N by two step sizes and storing a result of the incrementing of the value of the memory cell of rank k modulo N by two step sizes in a memory cell of the N memory cells of rank k+1 modulo N, wherein,

N is an integer greater than or equal to five,
k is an integer, and
i is an integer between 2 and N−3.

11. The method of claim 10 , wherein the value complementary to the null value is a value of a memory cell of the N memory cells after the memory cell is erased.

12. The method of claim 10 , wherein the memory cells of ranks lower than k−1 modulo N and of ranks higher than k+i+1 modulo N all represent values different from the value complementary to the null value.

13. The method of claim 10 , wherein the monotonic counter represents the null value when a memory cell of the N memory cells representing the null value is followed in rank by i memory cells representing the value complementary to the null value.

14. The method of claim 10 , wherein i is two.

15. The method of claim 14 , comprising performing an initialization operation, wherein in response to memory cells of the N memory cells of consecutive ranks between k modulo N and k+2 modulo N representing the value complementary to the null value, the initialization operation includes:
writing the null value in the memory cell of rank k+2 modulo N;
erasing the memory cell of rank k+3 modulo N;
writing any value different from the value complementary to the null value, in the memory cell of rank k+1 modulo N; and
erasing the memory cell of rank k+4 modulo N.

16. The method of claim 15 , wherein the writing any value different from the value complementary to the null value, in the memory cell of rank k+1 modulo N, comprises writing the zero value in the memory cell of rank K+1 modulo N.

17. The method of claim 15 , wherein in response to memory cells of the N memory cells of consecutive ranks between k+1 modulo N and k+3 modulo N represent the value complementary to the null value, the initialization operation includes:
writing the null value in the memory cell of rank k+2 modulo N;
writing any value different from the value complementary to the null value in the memory cell of rank k+1 modulo N; and
erasing the value of the memory cell of rank k+4 modulo N.

18. A system, comprising:
a processor, which, in operation, processes data; and
a monotonic counter coupled to the processor, wherein the monotonic counter, in operation:
stores a number N of binary words in N memory cells of a non-volatile memory, the N binary words representing a value of a monotonic counter, each binary word having a size sufficient to store a maximum value of the monotonic counter; and
responds to an indication to increment the value of the monotonic counter by a step size by:
in response to i memory cells of the N memory cells of consecutive ranks between k modulo N and k+i modulo N each representing a value complementary to a null value, erasing a value of a memory cell of the N memory cells of rank k+i+1 modulo N; and
in response to i+1 memory cells of the N memory cells of consecutive ranks betwe

Assignees

• Proton World Int Nv

Inventors

• Peeters Michael
• Modave Jean-Louis
• Van Keer Ronny

Classifications

• G11C8/04 Primary

  using a sequential addressing device, e.g. shift register, counter · CPC title

• G11C7/20

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

• H03K21/403 Primary

  Arrangements for storing the counting state in case of power supply interruption · CPC title

• H03K23/004

  Counters counting in a non-natural counting order, e.g. random counters · CPC title