Fault detection display apparatus and operation method thereof

Patent metadata

Field	Value
Publication number	US-11715399-B2
Application number	US-202217701065-A
Country	US
Kind code	B2
Filing date	Mar 22, 2022
Priority date	Jul 21, 2021
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

Disclosed is integrated circuit panel which detects fault of a driving circuit. The integrated circuit panel includes: a driving circuit array including first and second driving circuits; a data driver configured to output first and second input data signals through first and second data lines, respectively; a switch driver configured to output a switching signal through a switch line; and an error detection driver configured to receive first and second output data signals through first and second test lines, respectively, wherein, in response to the switching signal, the first and second driving circuits are configured to output the first and second output data signals, which are based on the first and second input data signal, through the first and second test lines, respectively, and the error detection driver is configured to detect a fault of the first or second driving circuit based on the first or second output data signal.

First claim

What is claimed is:

1. An integrated circuit panel for detecting a fault of a driving circuit which controls a display panel, the integrated circuit panel comprising:
a driving circuit array comprising a first driving circuit and a second driving circuit;
a data driver configured to output a first input data signal through a first data line, and output a second input data signal through a second data line;
a switch driver configured to output a first switching signal through a first switch line; and
an error detection driver configured to receive a first output data signal through a first test line, and receive a second output data signal through a second test line,
wherein, in response to the first switching signal, the first driving circuit is configured to output the first output data signal, which is based on the first input data signal, through the first test line, and the second driving circuit is configured to output the second output data signal, which is based on the second input data signal, through the second test line, and
wherein the error detection driver is configured to detect a fault of the first driving circuit based on the first output data signal, and detect a fault of the second driving circuit based on the second output data signal.

2. The integrated circuit panel of claim 1 , further comprising a line driver configured to output a first clock signal through a first clock line,
wherein, in response to the first clock signal, the first driving circuit is configured to store the first input data signal, and the second driving circuit is configured to store the second input data signal.

3. The integrated circuit panel of claim 2 , wherein the data driver is further configured to output the first input data signal and the second input data signal to the error detection driver not by way of the driving circuit array,
wherein the line driver is further configured to output the first clock signal to the error detection driver, and
wherein the error detection driver is configured to detect the fault of the first driving circuit by comparing the received first output data signal with the first input data signal and the first clock signal, and detect the fault of the second driving circuit by comparing the second output data signal with the received second input data signal and the first clock signal.

4. The integrated circuit panel of claim 1 , wherein the first driving circuit is configured to generate a first driving signal controlling a corresponding pixel circuit included in the display panel based on the first input data signal, and the second driving circuit is configured to generate a second driving signal controlling a corresponding pixel circuit the display panel based on the second input data signal.

5. The integrated circuit panel of claim 4 , wherein the first driving signal is generated by performing an AND operation on the first input data signal and a first pulse width modulation (PWM) signal, and the second driving signal is generated by performing an AND operation on the second input data signal and a second PWM signal.

6. The integrated circuit panel of claim 4 , wherein the first driving circuit is configured to output the first output data signal through the first test line during the generation of the first driving signal.

7. The integrated circuit panel of claim 1 , wherein the driving circuit array further comprises a third driving circuit and a fourth driving circuit,
wherein the switch driver is further configured to output a second switching signal through a second switch line,
wherein, in response to the second switching signal, the third driving circuit is configured to output a third output data signal, which is based on the first input data signal, through the first test line, and the fourth driving circuit is configured to output a fourth output data signal, which is based on the second input data signal, through the second test line, and
wherein the error detection driver is configured to detect a fault of the third driving circuit based on the third output data signal, and detect a fault of the fourth driving circuit based on the fourth output data signal.

8. The integrated circuit panel of claim 7 , further comprising a line driver configured to output a first clock signal through a first clock line, and output a second clock signal through a second clock line,
wherein, in response to the first clock signal, the first driving circuit and the second driving circuit are configured to store the first input data signal and the second input data signal, respectively, and
wherein, in response to the second clock signal, the third driving circuit and the fourth driving circuit are configured to store the first input data signal and the second input data signal, respectively.

9. The integrated circuit panel of claim 8 , wherein the line driver outputs the first clock signal and the second clock signal at different time periods.

10. The integrated circuit panel of claim 7 , wherein a time period in which the switch driver is configured to output the first switching signal is different from a time period in which the switch driver is configured to output the second switching signal.

11. An operation method of an integrated circuit panel for detecting a fault of a driving circuit which controls a display panel, the method comprising:
providing a first input data signal to a first driving circuit, and providing a second input data signal to a second driving circuit;
providing a first switching signal to the first driving circuit and the second driving circuit;
in response to the first switching signal, outputting, by the first driving circuit, a first output data signal which is based on the first input data signal, and outputting, by the second driving circuit, a second output data signal which is based on the second input data signal; and
determining whether a fault occurs in the first driving circuit based on the first output data signal, and determining whether a fault occurs in the second driving circuit based on the second output data signal.

12. The method of claim 11 , further comprising:
providing the first input data signal to a third driving circuit, and providing the second input data signal to a fourth driving circuit;
providing a second switching signal to the third driving circuit and the fourth driving circuit;
in response to the second switching signal, outputting, by the third driving circuit, a third output data signal which is based on the first input data signal, and outputting, by the fourth driving circuit, a fourth output data signal which is based on the second input data signal; and
determining whether a fault occurs in the third driving circuit based on the third output data signal, and determining whether a fault occurs in the fourth driving circuit based on the fourth output data signal.

13. The method of claim 12 , further comprising:
providing a first clock signal to the first driving circuit and the second driving circuit;
providing a second clock signal to the third driving circuit and the fourth driving circuit;
storing, by the first driving circuit, the first input data signal, and storing, by the second driving circuit, the second input data signal are performed, in response to the first clock signal; and
storing, by the third driving circuit, the first input data signal, and storing, by the fourth driving circuit, the second input data signal, in response to the second clock signal.

14. The method of claim 13 , wherein the providing the first clock signal and the providing the second clock signal are performed at different time periods.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Yilho
• Kwon Yongil
• Kang Sugyeung
• Kwon Tae-Hyeon
• Kim Sunkwon
• Park Hyunsang
• Song Uijong

Classifications

• G09G3/006 Primary

  Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

• G09G3/32

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G2330/12

  Test circuits or failure detection circuits included in a display system, as permanent part thereof · CPC title

• G09G2310/027

  Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters · CPC title

• G09G3/2014

  by modulation of the duration of a single pulse during which the logic level remains constant · CPC title