Heater structure configured to improve thermal efficiency in a modulator device

Patent metadata

Field	Value
Publication number	US-11714299-B2
Application number	US-202117556006-A
Country	US
Kind code	B2
Filing date	Dec 20, 2021
Priority date	Oct 30, 2019
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a waveguide and a heater structure. The waveguide is disposed on a substrate and comprises an active region that extends continuously along a first distance. The heater structure overlies the waveguide. The heater structure comprises a conductive structure over the active region and a vertical structure disposed between the conductive structure and the substrate. The vertical structure comprises a conductive upper vertical segment and a lower vertical segment. The conductive structure and the conductive upper vertical segment continuously laterally extend across a second distance that is greater than or equal to the first distance. The first distance is greater than a width of the conductive structure.

First claim

What is claimed is:

1. An integrated chip, comprising:
a waveguide disposed on a substrate and comprising an active region that extends continuously along a first distance; and
a heater structure overlying the waveguide, wherein the heater structure comprises a conductive structure over the active region and a vertical structure disposed between the conductive structure and the substrate, wherein the vertical structure comprises a conductive upper vertical segment and a lower vertical segment, wherein the lower vertical segment comprises a material different than that of the conductive upper vertical segment, and wherein the heater structure is configured to direct heat from the conductive structure towards the waveguide via the lower vertical segment and the conductive upper vertical segment.

2. The integrated chip of claim 1 , wherein the active region comprises a first doped region that continuously extends along the first distance.

3. The integrated chip of claim 2 , wherein the conductive structure and the conductive upper vertical segment continuously laterally extend across a second distance that is greater than or equal to the first distance, wherein the conductive upper vertical segment comprises a metal via and a metal wire that continuously laterally extend along the second distance in an unbroken path.

4. The integrated chip of claim 3 , wherein a thickness of the conductive structure is less than a thickness of the metal wire.

5. The integrated chip of claim 1 , wherein a top surface of the vertical structure directly contacts a bottom surface of the conductive structure.

6. The integrated chip of claim 1 , wherein a width of the vertical structure discretely decreases at a first point below a bottom surface of the conductive structure and discretely increases at a second point below the first point, wherein the width of the vertical structure continuously decreases along a vertical distance between the first point and the second point.

7. The integrated chip of claim 1 , further comprising:
a conductive via disposed over and contacting the conductive structure, wherein the conductive via has a first thermal conductivity, the conductive structure has a second thermal conductivity less than the first thermal conductivity, the conductive upper vertical segment has the first thermal conductivity, and the lower vertical segment has a third thermal conductivity greater than the second thermal conductivity.

8. The integrated chip of claim 7 , wherein the conductive via and the conductive upper vertical segment respectively comprise a same metal material.

9. The integrated chip of claim 1 , further comprising: a conductive via over the substrate and laterally offset from the heater structure, wherein a bottom surface of the conductive via is aligned with a bottom surface of the conductive structure.

10. An integrated chip, comprising:
a waveguide overlying a substrate, wherein the waveguide comprises an active region configured to modulate light; and
a heater structure overlying the waveguide, wherein the heater structure comprises an upper conductive structure, an upper pillar structure below the upper conductive structure, and a lower pillar structure below the upper conductive structure, wherein the lower pillar structure has a thermal conductivity different than that of the upper pillar structure, wherein the heater structure is configured to direct heat from the upper conductive structure through the upper pillar structure and the lower pillar structure in a direction towards the active region.

11. The integrated chip of claim 10 , wherein a conductive via directly overlies the active region and contacts the upper conductive structure, wherein the heater structure is configured to direct heat from the conductive via to the upper conductive structure in the direction towards the active region.

12. The integrated chip of claim 11 , wherein the conductive via and the upper pillar structure respectively comprise a first material, wherein the upper conductive structure comprises a second material different than the first material.

13. The integrated chip of claim 10 , wherein the heater structure is disposed on opposing sides of the active region and over a top surface of the active region, and wherein the heater structure is configured to confine heat to a region around the active region.

14. The integrated chip of claim 10 , wherein the lower pillar structure and the waveguide respectively comprise a semiconductor material, and wherein the lower pillar structure is completely laterally separated from the waveguide by a dielectric structure that comprises a material different than the semiconductor material.

15. The integrated chip of claim 14 , wherein the dielectric structure directly contacts and continuously extends from an inner sidewall of the lower pillar structure to an outermost sidewall of the waveguide.

16. A method for forming an integrated chip, the method comprising:
forming a waveguide over a substrate, wherein the waveguide comprises an active region;
forming a pillar structure over the substrate, wherein the active region is spaced laterally between sidewalls of the pillar structure, wherein the pillar structure comprises an upper pillar structure overlying a lower pillar structure, wherein the lower pillar structure comprises a material different than that of the upper pillar structure; and
forming an upper conductive structure over the pillar structure and the waveguide, thereby defining a heater structure, wherein the heater structure is configured to direct heat from the upper conductive structure through the upper pillar structure and the lower pillar structure in a direction towards the active region.

17. The method of claim 16 , wherein forming the waveguide and the pillar structure comprises:
forming a device layer over a bulk dielectric structure, wherein the bulk dielectric structure is disposed on the substrate; and
performing an etch process on the device layer to define the waveguide and the lower pillar structure, wherein the etch process exposes a top surface of the bulk dielectric structure in a region directly between an outer sidewall of the waveguide and an inner sidewall of the lower pillar structure.

18. The method of claim 17 , wherein the etch process completely removes material of the device layer from the region.

19. The method of claim 17 , further comprising:
forming a dielectric structure over the substrate, wherein the dielectric structure is disposed within the region, and wherein the dielectric structure has a bottom surface within the region that is aligned with a bottom surface of the lower pillar structure.

20. The method of claim 16 , further comprising:
forming an etch stop layer over the upper conductive structure such that the etch stop layer continuously extends from opposing sidewalls of the upper conductive structure to a top surface of the upper conductive structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Shih-Wei
• Liu Ming Chyi

Classifications

• G02F1/011 Primary

  in optical waveguides, not otherwise provided for in this subclass · CPC title

• G02F1/0147 Primary

  based on thermo-optic effects (G02F1/132 takes precedence) · CPC title

• G02F1/2257

  the optical waveguides being made of semiconducting material · CPC title

• G02B2006/12142

  Modulator · CPC title

• G02F2203/50

  Phase-only modulation · CPC title