Integrated optoelectronic device with heater

US10739622B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10739622-B2
Application numberUS-201816235197-A
CountryUS
Kind codeB2
Filing dateDec 28, 2018
Priority dateDec 28, 2018
Publication dateAug 11, 2020
Grant dateAug 11, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed are structures as well as methods of manufacture and operation of integrated optoelectronic devices that facilitate directly heating the diode or waveguide structures to regulate a temperature of the device while allowing electrical contacts to be placed close to the device to reduce the electrical resistance. Embodiments include, in particular, heterogeneous electro-absorption modulators that include a compound-semiconductor diode structure placed above a waveguide formed in the device layer of an SOI substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. An integrated optoelectronic device comprising: a semiconductor substrate; a diode structure formed above the substrate, the diode structure comprising a bottom diode strip and, formed on top of the bottom diode strip, a layered diode mesa comprising an intrinsic-type layer and a top diode layer; a first electrical connection contacting the top diode layer of the diode mesa, the first electrical connection connected to a first electrical node of an electronic circuit; and second and third electrical connections contacting the bottom diode strip on opposite respective sides of the diode mesa, the second electrical connection connected to a second electrical node of the electronic circuit and the third electrical connection connected to a third electrical node of the electronic circuit. 2. The device of claim 1 , wherein the electronic circuit is operatively to apply a heater bias voltage between the second and third nodes and a reverse bias voltage across the diode structure corresponding to a non-zero average of a voltage between the first node and the second node and a voltage between the first node and the third node. 3. The device of claim 1 , wherein the electronic circuit is operatively to further apply an RF signal voltage at the first node. 4. The device of claim 1 , wherein the substrate is a semiconductor-on-insulator (SOI) substrate, the device further comprising a waveguide formed in a device layer of the SOI substrate underneath the diode structure. 5. The device of claim 4 , wherein the diode structure is made of a compound semiconductor material, the waveguide and diode mesa collectively forming a heterogeneous optical waveguide structure. 6. The device of claim 5 , wherein the waveguide is made of silicon and the diode structure is made of a III-V material. 7. The device of claim 4 , further comprising at least one of one or more thermal isolation channels formed in the device layer on both sides of the diode mesa or a thermally isolating etched region formed in a handle of the SOI substrate underneath the diode structure. 8. The device of claim 1 , wherein the device is an electro-absorption modulator. 9. An integrated optoelectronic device comprising: a semiconductor-on-insulator (SOI) substrate; a heterogeneous optical waveguide structure comprising a waveguide formed in a device layer of the SOI substrate and a layered compound-semiconductor structure formed above the waveguide, the compound-semiconductor structure comprising a doped bottom strip and, formed on top of the doped bottom strip, a layered mesa comprising an intrinsic-type layer and a doped top layer; a first electrical connection contacting the doped top layer of the layered mesa, the first electrical connection connected to a first electrical node; one or more second electrical connections contacting the doped bottom strip, the one or more second electrical connections connected to a second electrical node; and third and fourth electrical connections contacting the device layer of the SOI substrate on opposite respective sides of the waveguide, the third and fourth electrical connections being connected to third and fourth electrical nodes, respectively. 10. The device of claim 9 , wherein the layered compound-semiconductor structure is a diode structure. 11. The device of claim 10 , wherein the first and second electrical nodes are part of a first electronic circuit that is operatively to apply a reverse bias voltage across the diode structure between the first and second nodes, and wherein the third and fourth electrical nodes are part of a second electronic circuit that is operatively to apply a heater bias voltage between the third and fourth nodes. 12. The device of claim 9 , further comprising at least one of one or more thermal isolation channels formed in the device layer on both sides of the waveguide and mesa or a thermally isolating etched region formed in a handle of the SOI substrate underneath the heterogeneous optical waveguide structure. 13. The device of claim 9 , wherein the waveguide is made of silicon and the diode structure is made of a III-V material. 14. The device of claim 9 , wherein the third and fourth electrical connections are spaced apart along an axis of the waveguide. 15. The device of claim 9 , wherein the device is an electro-absorption modulator.

Assignees

Inventors

Classifications

  • Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title

  • having three or more elements, e.g. GaAlAs, InGaAs or InGaAsP · CPC title

  • Interconnections · CPC title

  • H10F30/20Primary

    the devices having potential barriers, e.g. phototransistors · CPC title

  • using electro-absorption effects, e.g. Franz-Keldysh [FK] effect or quantum confined stark effect [QCSE] · CPC title

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What does patent US10739622B2 cover?
Disclosed are structures as well as methods of manufacture and operation of integrated optoelectronic devices that facilitate directly heating the diode or waveguide structures to regulate a temperature of the device while allowing electrical contacts to be placed close to the device to reduce the electrical resistance. Embodiments include, in particular, heterogeneous electro-absorption modula…
Who is the assignee on this patent?
Juniper Networks Inc
What technology area does this patent fall under?
Primary CPC classification H10F30/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 11 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).