Integrated multi-die partitioned voltage regulator

Patent metadata

Field	Value
Publication number	US-11710720-B2
Application number	US-201816022515-A
Country	US
Kind code	B2
Filing date	Jun 28, 2018
Priority date	Jun 28, 2018
Publication date	Jul 25, 2023
Grant date	Jul 25, 2023

Abstract

A semiconductor package is provided, which includes a first die and a second die. The first die includes a first section of a power converter, and the second die includes a second section of the power converter. The power converter may include a plurality of switches, and a Power Management (PM) circuitry to control operation of the power converter by controlling switching of the plurality of switches. The PM circuitry may include a first part and a second part. The first section of the power converter in the first die may include the first part of the PM circuitry, and the second section of the power converter in the second die may include the second part of the PM circuitry.

First claim

We claim:

1. An apparatus, comprising:
a first die in a semiconductor package, the first die comprising a first section of a power converter; and
a second die in the semiconductor package, the second die comprising a second section of the power converter,
wherein the power converter comprises a plurality of switches, and power management (PM) circuitry to control operation of the power converter by controlling switching of the plurality of switches,
wherein the PM circuitry comprises a first part and a second part,
wherein the first section of the power converter in the first die comprises the first part of the PM circuitry, and
wherein the second section of the power converter in the second die comprises the second part of the PM circuitry, wherein the PM circuitry comprises a plurality of sense circuitries, wherein an individual sense circuitry of the plurality of sense circuitries is to sense one or both of a voltage or a current of a corresponding switch of the plurality of switches, wherein the first part of the PM circuitry in the first die comprises a first subset of the plurality of sense circuitries, and wherein the second part of the PM circuitry in the second die comprises a second subset of the plurality of sense circuitries.

2. The apparatus of claim 1 , wherein the PM circuitry comprises:
a controller, wherein the first subset of the plurality of sense circuitries in the first die is to sense the voltage or current, and wherein the second subset of the plurality of sense circuitries in the second die is to transmit the voltage or current to the controller.

3. The apparatus of claim 2 , wherein the second subset comprises an analog to digital converter (ADC) to digitalize the sensed voltage or current for transmission to the controller.

4. The apparatus of claim 1 , wherein:
the first section of the power converter in the first die comprises a first subset of the plurality of switches; and
the second section of the power converter in the second die comprises a second subset of the plurality of switches.

5. The apparatus of claim 1 , wherein the PM circuitry comprises:
a plurality of driver circuitries, wherein an individual driver circuitry of the plurality of driver circuitries is to drive a corresponding switch of the plurality of switches,
wherein the first section of the power converter in the first die comprises includes a first subset of the plurality of driver circuitries, and
wherein the second section of the power converter in the second die comprises includes a second subset of the plurality of driver circuitries.

6. The apparatus of claim 1 , comprising:
a substrate, wherein at least one of the first or second dies is on the substrate,
wherein the power converter comprises a plurality of passive components, and
wherein one or more of the plurality of passive components are on, or embedded within, the substrate.

7. The apparatus of claim 1 , wherein the power converter is a first power converter, and the semiconductor package further comprises a third die comprising a third section of a second power converter, wherein one of the first die or the second die comprises a fourth section of the second power converter.

8. The apparatus of claim 1 , further comprising:
a power supply to supply power to the semiconductor package.

9. An apparatus, comprising:
a first die in a semiconductor package, the first die comprising a first section of a power converter; and
a second die in the semiconductor package, the second die comprising a second section of the power converter,
wherein the power converter comprises a plurality of switches, and power management (PM) circuitry to control operation of the power converter by controlling switching of the plurality of switches,
wherein the PM circuitry comprises a first part and a second part, a controller, and a feedback circuitry to measure an output voltage of the power converter, and transmit the measured voltage to the controller, the first section comprises the first part, and the second section comprises the second part,
wherein the first part of the PM circuitry in the first die comprises a first portion of the feedback circuitry, which is to measure the output voltage; and
wherein the second part of the PM circuitry in the second die comprises a second portion of the feedback circuitry, which is to digitalize the measurement of the output voltage and transmit the digitalized measurement of the output voltage to the controller.

10. The apparatus of claim 9 , wherein the PM circuitry comprises:
a plurality of analog components; and
a plurality of digital components,
wherein the first part of the PM circuitry in the first die includes the plurality of analog components; and
wherein the second part of the PM circuitry in the second die includes the plurality of digital components.

11. The apparatus of claim 9 , wherein:
the first section of the power converter in the first die comprises a first subset of the plurality of switches; and
the second section of the power converter in the second die comprises a second subset of the plurality of switches.

12. The apparatus of claim 9 , wherein the PM circuitry comprises:
a plurality of driver circuitries, wherein an individual driver circuitry of the plurality of driver circuitries is to drive a corresponding switch of the plurality of switches,
wherein the first section of the power converter in the first die comprises a first subset of the plurality of driver circuitries, and
wherein the second section of the power converter in the second die comprises a second subset of the plurality of driver circuitries.

13. The apparatus of claim 9 , comprising:
a substrate, wherein at least one of the first or second dies is on the substrate,
wherein the power converter comprises a plurality of passive components, and
wherein one or more of the plurality of passive components are on, or embedded within, the substrate.

14. The apparatus of claim 9 , further comprising:
a power supply to supply power to the semiconductor package.

15. An apparatus, comprising:
a first die in a semiconductor package, the first die comprising a first section of a power converter;
a second die in the semiconductor package, the second die comprising a second section of the power converter; and
a substrate, wherein one or more passive components of the power converter are on, or embedded within, the substrate,
wherein the substrate has a first side and a second side that is opposite the first side,
wherein the substrate has a recess on the first side,
wherein the first die is at least in part within the recess on the first side of the substrate,
wherein the second die is on the second side of the substrate or stacked on the first die,
wherein the power converter comprises a plurality of switches, and power management (PM) circuitry to control operation of the power converter by controlling switching of the plurality of switches, and
wherein the PM circuitry comprises a first part and a second part,
wherein the first section of the power converter in the first die comprises the first part of the PM circuitry, and
wherein the second section of the power converter in the second die comprises the second part of the PM circuitry.

16. The apparatus of claim 15 , wherein:
the recess is a first recess; and
the substrate has a second recess on the first side,
wherein the first die is at least in part within the second recess on the first side of the substrate.

17. The apparatus of claim 15 , wherein the power converter is a first power conv

Assignees

• Intel Corp

Inventors

• Choi Beomseok
• Kulasekaran Siddharth
• Radhakrishnan Kaladhar

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title