Semiconductor device having antenna on chip package and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11705409-B2
Application number	US-202016916066-A
Country	US
Kind code	B2
Filing date	Jun 29, 2020
Priority date	Apr 30, 2018
Publication date	Jul 18, 2023
Grant date	Jul 18, 2023

Abstract

A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a chip package;
a dielectric structure disposed on the chip package, the dielectric structure comprising a first layer, a second layer disposed between the chip package and the first layer and comprising a cavity, and a vent in communication with the cavity, wherein the first layer covers the cavity, wherein the vent is an air vent; and
a first antenna pattern disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.

2. The semiconductor device according to claim 1 , further comprising:
a second antenna pattern disposed inside the cavity of the dielectric structure, wherein the chip package is electrically coupled to the second antenna pattern.

3. The semiconductor device according to claim 2 , wherein the first antenna pattern is disposed on the first layer of the dielectric structure and right above the second antenna pattern.

4. The semiconductor device according to claim 1 , wherein the first antenna pattern is disposed on the first layer and located outside the cavity.

5. The semiconductor device according to claim 1 , wherein the vent is at the first layer or at the second layer.

6. The semiconductor device according to claim 1 , wherein the chip package comprises:
a chip;
an encapsulant encapsulating the chip; and
a redistribution layer disposed on the chip and the encapsulant and electrically connected to the chip.

7. The semiconductor device according to claim 6 , wherein the chip package further comprises an insulating layer disposed on the redistribution layer and located opposite to the encapsulant, the semiconductor device further comprises a second antenna pattern disposed on the insulating layer, and the chip package is electrically coupled to the second antenna pattern.

8. A semiconductor device, comprising:
a chip package;
a dielectric structure disposed on the chip package and comprising:
a dielectric layer; and
a molding layer interposed between the dielectric layer and the chip package; and

a first antenna pattern disposed on the dielectric layer of the dielectric structure and corresponding to a cavity of the molding layer, wherein the chip package is electrically coupled to the first antenna pattern.

9. The semiconductor device according to claim 8 , wherein a through hole of the dielectric layer is in communication with the cavity of the molding layer, and the first antenna pattern is disposed next to the through hole.

10. The semiconductor device according to claim 8 , wherein the molding layer of the dielectric structure is in physical contact with a redistribution layer of the chip package.

11. The semiconductor device according to claim 8 , further comprising:
a second antenna pattern disposed on an insulating layer of the chip package, located within the cavity of the molding layer of the dielectric structure, and electrically coupled to the chip package.

12. The semiconductor device according to claim 8 , wherein the chip package comprises:
a chip;
an encapsulant encapsulating the chip; and
a redistribution layer disposed on the chip and the encapsulant and electrically connected to the chip, wherein the molding layer of the dielectric structure is disposed over the redistribution layer of the chip package and opposite to the encapsulant.

13. The semiconductor device according to claim 8 , wherein the cavity of the molding layer is tapered toward the chip package.

14. The semiconductor device according to claim 8 , wherein a vent runs sideways through the molding layer to vent the cavity.

15. A semiconductor device, comprising:
a chip encapsulated by an encapsulant;
a first redistribution layer disposed on the chip and the encapsulant and electrically coupled to the chip;
a molding layer disposed over the first redistribution layer and located opposite to the chip and the encapsulant;
a dielectric layer overlying the molding layer and located opposite to the first redistribution layer, the dielectric layer covering a cavity of the molding layer; and
a first antenna pattern overlying the dielectric layer and located opposite to the cavity of the molding layer, wherein the chip is electrically coupled to the first antenna pattern.

16. The semiconductor device according to claim 15 , wherein a through hole of the dielectric layer is in communication with the cavity of the molding layer, and the first antenna pattern is disposed next to the through hole.

17. The semiconductor device according to claim 15 , further comprising:
a polymer layer interposed between the first redistribution layer and the molding layer; and
a second antenna pattern overlying the polymer layer, located within the cavity of the molding layer, and electrically coupled to the chip.

18. The semiconductor device according to claim 15 , further comprising:
a second redistribution layer in contact with an active surface of the chip, wherein a back surface of the chip is attached to the first redistribution layer; and
a through molding via penetrating through the encapsulant, wherein the chip is electrically coupled to the first redistribution layer through the second redistribution layer and the through molding via.

19. The semiconductor device according to claim 15 , wherein the cavity of the molding layer is tapered toward the first redistribution layer.

20. The semiconductor device according to claim 15 , wherein a lateral vent of the molding layer is in communication with the cavity of the molding layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wan Albert
• Hsieh Ching-Hua
• Shih Chao-Wen
• Pu Han-Ping
• Chen Meng-Tse
• Chiu Sheng-Hsiang

Classifications

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W44/248

  for antennas · CPC title