Core fill to reduce dishing and metal pillar fill to increase metal density of interconnects

Patent metadata

Field	Value
Publication number	US-11705395-B2
Application number	US-201816017962-A
Country	US
Kind code	B2
Filing date	Jun 25, 2018
Priority date	Jun 25, 2018
Publication date	Jul 18, 2023
Grant date	Jul 18, 2023

Abstract

An integrated circuit structure comprises a first and second conductive structures formed in an interlayer dielectric (ILD) of a metallization stack over a substrate. The first conductive structure comprises a first conductive line, and first dummy structures located adjacent to one or more sides of the first conductive line, wherein the first dummy structures comprise respective arrays of dielectric core segments having a Young's modulus larger than the Young's modulus of the ILD, the dielectric core segments being approximately 1-3 microns in width and spaced apart by approximately 1-3 microns. The second conductive structure formed in the ILD comprises a conductive surface and second dummy structures formed in the conductive surface, where the second dummy structures comprising an array of conductive pillars.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a first conductive structure formed in an interlayer dielectric (ILD) of a metallization stack over a substrate, the first conductive structure comprising a first conductive line, and first linerless dummy structures located adjacent to one or more sides of the first conductive line, wherein the first linerless dummy structures are located in a first metal layer (Mn) and comprise respective arrays of dielectric core segments having a Young's modulus larger than the Young's modulus of the ILD, the respective arrays of dielectric core segments being approximately 1-3 microns in width and spaced apart by approximately 1-3 microns, wherein the respective arrays of dielectric core segments of the first conductive structure propagate in a direction parallel to sides of the first conductive line; and
a second conductive structure formed in the ILD, the second conductive structure comprising a conductive surface and second dummy structures formed in the conductive surface, the second dummy structures are located in a second metal layer (Mn−1) beneath the first metal layer (Mn) and comprise an array of conductive pillars.

2. The integrated circuit structure of claim 1 , wherein the first linerless dummy structures are located adjacent to two or more sides of the first conductive line.

3. The integrated circuit structure of claim 1 , wherein the first linerless dummy structures comprise: a first array of the dielectric core segments adjacent to one side of the first conductive line and a second array of the dielectric core segments adjacent to an opposite side of the first conductive line.

4. The integrated circuit structure of claim 1 , wherein the first linerless dummy structures are located adjacent to each of the sides of the first conductive line.

5. The integrated circuit structure of claim 1 , further comprising multiple conductive lines, and wherein the first linerless dummy structures are located adjacent to each of the multiple conductive lines.

6. The integrated circuit structure of claim 1 , wherein the conductive surface of the second conductive structure comprises a first metal material and the array of conductive pillars comprise a second metal material.

7. The integrated circuit structure of claim 6 , wherein the first metal material and the second metal material are a same metal material.

8. The integrated circuit structure of claim 6 , wherein the first metal material and the second metal material are a different metal material.

9. The integrated circuit structure of claim 6 , wherein the first metal material and the second metal material comprise copper, cobalt or tungsten.

10. The integrated circuit structure of claim 6 , wherein the second conductive structure further comprises a conductive border surrounding sides of the conductive surface.

11. The integrated circuit structure of claim 6 , wherein a conductive border comprises a same second metal material as the array of conductive pillars.

12. The integrated circuit structure of claim 6 , further comprising a liner formed along sides and bottom of the array of conductive pillars.

13. The integrated circuit structure of claim 12 , wherein the liner comprises tantalum, tantalum nitride, titanium, titanium nitride, aluminum oxide, manganese, or manganese nitride.

14. The integrated circuit structure of claim 6 , wherein the array of conductive pillars are approximately 2×2 microns and a minimum size of a planar conductive surface is approximately 25×25 microns.

15. The integrated circuit structure of claim 1 , wherein the ILD comprises silicon oxide or a carbon-doped silicon oxide film.

Assignees

• Intel Corp

Inventors

• Lin Kevin

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/076

  in via holes or trenches · CPC title