Vias for package substrates

Patent metadata

Field	Value
Publication number	US-11705389-B2
Application number	US-201916437420-A
Country	US
Kind code	B2
Filing date	Jun 11, 2019
Priority date	Jun 11, 2019
Publication date	Jul 18, 2023
Grant date	Jul 18, 2023

Abstract

Embodiments herein describe techniques for a semiconductor device including a package substrate. The package substrate includes a via pad at least partially in a core layer. A first dielectric layer having a first dielectric material is above the via pad and the core layer, where the first dielectric layer has a first through hole that is through the first dielectric layer to reach the via pad. A second dielectric layer having a second dielectric material is at least partially filling the first through hole, where the second dielectric layer has a second through hole that is through the second dielectric layer to reach the via pad. A via is further within the second through hole of the second dielectric layer, surrounded by the second dielectric material, and in contact with the via pad. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An apparatus, comprising:
a via pad at least partially in a core layer;
a first dielectric layer having a first dielectric material above the via pad and the core layer, wherein the first dielectric layer has a first through hole that is through the first dielectric layer to reach the via pad;
a second dielectric layer having a second dielectric material at least partially filling the first through hole, wherein the second dielectric layer has a second through hole that is through the second dielectric layer to reach the via pad, and wherein the second dielectric layer has an uppermost surface; and
a via within the second through hole of the second dielectric layer, surrounded by the second dielectric material, and in contact with the via pad, wherein the via has an uppermost surface at a same level as the uppermost surface of the second dielectric layer.

2. The apparatus of claim 1 , wherein the first through hole has a bottom opening that is smaller width than a top opening.

3. The apparatus of claim 1 , wherein the second through hole has a bottom opening that is smaller width than a top opening.

4. The apparatus of claim 1 , wherein the first through hole or the second through hole has a rectangular cross section with a bottom opening substantially same as a top opening.

5. The apparatus of claim 1 , wherein a portion of the second dielectric layer is above the first dielectric layer.

6. The apparatus of claim 1 , wherein the second dielectric layer is coplanar with the first dielectric layer.

7. The apparatus of claim 1 , wherein the via includes a first via portion and a second via portion within the second dielectric layer, the first via portion is of a first shape, and the second via portion is of a second shape different from the first shape.

8. The apparatus of claim 1 , wherein the first dielectric material includes a glass-cloth material (GCM) impregnated within a dielectric material.

9. The apparatus of claim 8 , wherein the GCM has a coefficient of thermal expansion (CTE) in a range of about 8 to about 18.

10. The apparatus of claim 8 , wherein the first dielectric material includes a glass material, a resin material, and a filler material; and
the second dielectric material includes the resin material.

11. The apparatus of claim 10 , wherein the resin material is a build up resin material.

12. The apparatus of claim 10 , wherein the resin material includes FR-4-epoxy, polyfunctional FR-4, high temperature one component epoxy system, bismaleimide trizaine epoxy (BT), polyimide epoxy, cyanate ester (CE), polyimide, phenol hardener, phenolic ester hardener, or polyimide and polytetrafluoroethylene (PTFE).

13. The apparatus of claim 10 , wherein the glass material includes a non-woven glass material, a woven glass material, a fiber glass material, or a filled glass material; and
the filler material includes silicon dioxide, aluminum oxide, calcium oxide, magnesium oxide, boron trioxide, iron(iii) oxide, or zirconium oxide.

14. The apparatus of claim 1 , wherein the core layer includes organic resin, inorganic filler, or a conductive material.

15. The apparatus of claim 1 , wherein the via pad has a width of about 50 um to 150 um, the via has a width of about 10 um to about 100 um, the first dielectric layer has a thickness of about 10 um to 50 um.

16. A computing device, comprising:
a semiconductor die;
a printed circuit board (PCB); and
a package substrate between the semiconductor die and the PCB, wherein the package substrate includes:
a via pad at least partially in a core layer;
a first dielectric layer having a first dielectric material above the via pad and the core layer, wherein the first dielectric layer has a first through hole that is through the first dielectric layer to reach the via pad;
a second dielectric layer having a second dielectric material at least partially filling the first through hole, wherein the second dielectric layer has a second through hole that is through the second dielectric layer to reach the via pad, and wherein the second dielectric layer has an uppermost surface; and
a via within the second through hole of the second dielectric layer, surrounded by the second dielectric material, and in contact with the via pad, wherein the via has an uppermost surface at a same level as the uppermost surface of the second dielectric layer.

17. The computing device of claim 16 , wherein the first through hole has a bottom opening that is smaller than a top opening; or the second through hole has a bottom opening that is smaller than a top opening.

18. The method of claim 17 , wherein a portion of the second dielectric layer is above the first dielectric layer.

19. The computing device of claim 16 , wherein the first dielectric material includes a glass-cloth material (GCM) impregnated within a dielectric material, the GCM has a coefficient of thermal expansion (CTE) in a range of about 8 to about 18;
the first dielectric material includes a glass material, a resin material, and a filler material; and
the second dielectric material includes the resin material.

20. The computing device of claim 16 , wherein the computing device includes a device selected from the group consisting of a wearable device or a mobile computing device, the wearable device or the mobile computing device including one or more of an antenna, a touchscreen controller, a display, a battery, a processor, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, and a camera coupled with the memory device.

21. An apparatus, comprising:
a via pad at least partially in a core layer;
a first dielectric layer having a first dielectric material above the via pad and the core layer, wherein the first dielectric layer has a first through hole that is through the first dielectric layer to reach the via pad, wherein the first dielectric material includes a glass-cloth material (GCM) impregnated within a dielectric material, wherein the first dielectric material includes a glass material, a resin material, and a filler material;
a second dielectric layer having a second dielectric material at least partially filling the first through hole, wherein the second dielectric layer has a second through hole that is through the second dielectric layer to reach the via pad, wherein the second dielectric material includes the resin material; and
a via within the second through hole of the second dielectric layer, surrounded by the second dielectric material, and in contact with the via pad.

22. The apparatus of claim 21 , wherein the resin material is a build up resin material.

23. The apparatus of claim 21 , wherein the resin material includes FR-4-epoxy, polyfunctional FR-4, high temperature one component epoxy system, bismaleimide trizaine epoxy (BT), polyimide epoxy, cyanate ester (CE), polyimide, phenol hardener, phenolic ester hardener, or polyimide and polytetrafluoroethylene (PTFE).

24. The apparatus of claim 21 , wherein the glass material includes a non-woven glass material, a woven glass material, a fiber glass material, or a filled glass material; and
the filler material includes silicon dioxide, aluminum oxide, calcium oxide, magnesium oxide, boron trioxide, iron(iii) oxide, or zirconium oxide.

Assignees

• Intel Corp

Inventors

• Brown Andrew J
• Garner Luke
• Cheng Liwei
• Link Lauren
• Xu Cheng
• Wang Ying
• Zou Bin
• Zhang Chong

Classifications

• H10W70/095

  of vias therein · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10W70/695

  Organic materials · CPC title

• H10W70/635 Primary

  Through-vias · CPC title

• H01L23/49827 Primary

  Electricity · mapped topic