Method and storage system with a layered caching policy

Patent metadata

Field	Value
Publication number	US-11704236-B2
Application number	US-202117528390-A
Country	US
Kind code	B2
Filing date	Nov 17, 2021
Priority date	Nov 17, 2021
Publication date	Jul 18, 2023
Grant date	Jul 18, 2023

Abstract

A storage system has volatile memory for use as a cache and can extend the available caching space by using a host memory buffer (HMB) in a host. However, because accesses to the HMB involve going through a host interface, there may be latencies in accessing the HMB, To reduce access latencies, the storage system views the volatile memory and the HMB as a two-level cache. In one use case, the storage system decides whether to store a logical-to-physical address table in the volatile memory or in the HMB based on a prediction of the likelihood that the table will be updated. If the likelihood for an update is above a threshold, the table is stored in the volatile memory, thereby eliminating the access latencies that would be encountered if the table needs to be updated and is stored in the HMB.

First claim

What is claimed is:

1. A storage system comprising:
a non-volatile memory;
a volatile memory;
an interface configured to communicate with a host comprising a host memory buffer; and
a controller configured to:
receive, from the host, a memory access command comprising a logical address;
read, from the non-volatile memory, a logical-to-physical address table that contains the logical address received from the host;
predict a likelihood that an update will be made to the logical-to-physical address table;
in response to the likelihood being above a threshold, store the logical-to-physical address table in the volatile memory and use the logical-to-physical address table: stored in the volatile memory to translate the logical address received from the host to a physical address in the non-volatile memory; and
in response to the likelihood not being above the threshold:
store the logical-to-physical address table in the host memory buffer and use the logical-to-physical address table stored in the host memory buffer to translate the logical address received from the host to the physical address in the non-volatile memory;
update the logical-to-physical address table after it has been stored in the host memory buffer;
receive the updated logical-to-physical address table from the host memory buffer;
store the updated logical-to-physical address table in the volatile memory; and
perform a consolidation process using the updated logical-to-physical address table.

2. The storage system of claim 1 , wherein the predicting is based on a historic access pattern of logical addresses.

3. The storage system of claim 1 , wherein the predicting is based on a characteristic of a set of logical addresses comprising the logical address received from the host.

4. The storage system of claim 3 , wherein the set comprises a namespace.

5. The storage system of claim 3 , wherein the characteristic comprises endurance.

6. The storage system of claim 1 , wherein the likelihood is above the threshold in response to a priority command needing to access the logical-to-physical address table.

7. The storage system of claim 6 , wherein the priority command is from an urgent queue.

8. The storage system of claim 1 , wherein the likelihood is above the threshold in response to the logical address received from the host being associated with sequential data.

9. The storage system of claim 1 , wherein the interface comprises a peripheral component interconnect express (PCIe) interface.

10. The storage system of claim 1 , wherein the non-volatile memory comprises a three-dimensional memory.

11. In a storage system comprising a non-volatile memory and a volatile memory, wherein the storage system is in communication with a host comprising a host memory, a method comprising:
determining whether a likelihood that a logical-to-physical address page read from the non-volatile memory will be updated is above a threshold;
in response to determining that the likelihood is above the threshold, storing the logical-to-physical address page in the volatile memory;
in response to determining that the likelihood is not above the threshold, storing the logical-to-physical address page in the host memory;
updating the logical-to-physical address page after it has been stored in the host memory,
receiving the updated logical-to-physical address page from the host memory;
storing the updated logical-to-physical address page in the volatile memory; and
performing a consolidation process using the updated logical-to-physical address page.

12. The method of claim 11 , wherein the determining is based on a historic access pattern of logical addresses.

13. The method of claim 11 , wherein the determining is based on a performance characteristic.

14. The method of claim 11 , wherein the likelihood is based on whether the logical-to-physical address page is associated, at least in part, with sequential data.

15. The method of claim 11 , wherein the likelihood is based on whether a priority command needs to access the logical-to-physical address page.

16. A storage system comprising:
a non-volatile memory;
a volatile memory;
means for determining whether a likelihood that a logical-to-physical address page read from the non-volatile memory will be updated is above a threshold;
means for storing the logical-to-physical address page in the volatile memory in response to determining that the likelihood is above the threshold;
means for storing the logical-to-physical address page in a host memory in a host in response to determining that the likelihood is not above the threshold;
means for updating the logical-to-physical address page after it has been stored in the host memory;
means for receiving the updated logical-to-physical address page from the host memory;
means for storing the updated logical-to-physical address page in the volatile memory; and
means for performing a consolidation process using the updated logical-to-physical address page.

Assignees

• Western Digital Tech Inc

Inventors

• Muthiah Ramanathan
• Bhoopali Laxmi
• Kelner Vered
• Journo Jonathan

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F12/0882

  Page mode · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title