Data storage device using a host memory buffer for single-level cell storage and control method for non-volatile memory

Patent metadata

Field	Value
Publication number	US-10991422-B2
Application number	US-201916524113-A
Country	US
Kind code	B2
Filing date	Jul 28, 2019
Priority date	Sep 26, 2018
Publication date	Apr 27, 2021
Grant date	Apr 27, 2021

Abstract

High-efficiency control technology for non-volatile memory. A non-volatile memory has single level cells (SLCs) and multiple level cells (e.g., MLCs or TLCs) and is controlled by a controller. According to the controller at the device end, a host allocates a system memory to provide a host memory buffer (HMB). The controller at the device end uses the HMB to buffer write data issued by the host, and then flushes the write data from the HMB to multi-level cells of the non-volatile memory without passing single level cells of the non-volatile memory to reduce write amplification problems due to the frequent use of the single-level cells.

First claim

What is claimed is:

1. A data storage device, comprising:
a non-volatile memory, having single-level cells and multi-level cells; and
a controller, operating the non-volatile memory as requested by a host,
wherein:
the controller requests the host to allocate a system memory of the host to provide a host memory buffer;
the controller temporarily stores write data issued by the host in the host memory buffer;
the controller flushes the write data temporarily stored in the host memory buffer to the multi-level cells of the non-volatile memory without passing the single-level cells of the non-volatile memory;
the controller manages a mapping table to record logical addresses of data stored in the different memory cells of the host memory buffer;
according to a logical address of the write data, the controller searches the mapping table; and
when the logical address of the write data has been recorded in the mapping table, the controller uses the write data to overwrite a space in the host memory buffer that stores an old data version of the logical address.

2. The data storage device as claimed in claim 1 , wherein:
when the logical address of the write data has not been recorded in the mapping table, the controller programs the write data to a spare area of the host memory buffer for temporary storage of the write data and updates the mapping table.

3. The data storage device as claimed in claim 2 , wherein:
when data buffered in the host memory buffer reaches a preset amount, the controller flushes the data of the preset amount from the host memory buffer to the multi-level cells of the non-volatile memory without passing the single-level cells of the non-volatile memory.

4. The data storage device as claimed in claim 3 , wherein:
the preset amount is equal to a data amount controlled through one word line.

5. The data storage device as claimed in claim 1 , wherein:
the controller has a read and write data buffer; and
after retrieving the write data from the host memory buffer, the controller uses the read and write data buffer to buffer the retrieved write data and then writes the buffered write data to the multi-level cells of the non-volatile memory without passing the single-level cells of the non-volatile memory.

6. The data storage device as claimed in claim 5 , wherein:
when receiving a write command issued by the host that indicates the write data, the controller uses the read and write data buffer to buffer the write data and then uploads the write data from the read and write data buffer to the host memory buffer to be retrieved by the controller later.

7. The data storage device as claimed in claim 1 , wherein:
the controller manages a mapping table to record logical addresses of data stored in the different memory cells of the host memory buffer;
according to the logical address indicated in a read command issued by the host, the controller searches the mapping table; and
when the logical address indicated in the read command has been recorded in the mapping table, the controller retrieves the read data from the host memory buffer to answer the host.

8. The data storage device as claimed in claim 7 , wherein:
the controller has a read and write data buffer; and
the controller uses the read and write data buffer to buffer the read data retrieved from the host memory buffer to answer the host.

9. A non-volatile memory control method, comprising:
operating a non-volatile memory as requested by a host, wherein the non-volatile memory has single-level cells and multi-level cells;
requesting the host to allocate a system memory of the host to provide a host memory buffer;
temporarily storing write data issued by the host in the host memory buffer;
flushing the write data temporarily stored in the host memory buffer to the multi-level cells of the non-volatile memory without passing the single-level cells of the non-volatile memory;
managing a mapping table to record logical addresses of data stored in the different memory cells of the host memory buffer;
searching the mapping table according to a logical address of the write data; and
when the logical address of the write data has been recorded in the mapping table, using the write data to overwrite a space in the host memory buffer that stores an old data version of the logical address.

10. The non-volatile memory control method as claimed in claim 9 , further comprising:
when the logical address of the write data has not been recorded in the mapping table, programming the write data to a spare area of the host memory buffer for temporary storage of the write data and updating the mapping table.

11. The non-volatile memory control method as claimed in claim 10 , further comprising:
when data buffered in the host memory buffer reaches a preset amount, flushing the data of the preset amount from the host memory buffer to the multi-level cells of the non-volatile memory without passing the single-level cells of the non-volatile memory.

12. The non-volatile memory control method as claimed in claim 11 , wherein:
the preset amount is equal to a data amount controlled through one word line.

13. The non-volatile memory control method as claimed in claim 9 , further comprising:
providing a read and write data buffer at a device end; and
after retrieving the write data from the host memory buffer, using the read and write data buffer to buffer the retrieved write data and then writing the buffered write data to the multi-level cells of the non-volatile memory without passing the single-level cells of the non-volatile memory.

14. The non-volatile memory control method as claimed in claim 13 , wherein:
when receiving a write command indicating the write data and issued by the host that, using the read and write data buffer to buffer the write data and then uploading the write data from the read and write data buffer to the host memory buffer to be downloaded to the device end later.

15. The non-volatile memory control method as claimed in claim 9 , further comprising:
managing a mapping table to record logical addresses of data stored in the different memory cells of the host memory buffer;
searching the mapping table according to the logical address indicated in a read command issued by the host; and
when the logical address indicated in the read command has been recorded in the mapping table, retrieving the read data from the host memory buffer to answer the host.

16. The non-volatile memory control method as claimed in claim 15 , further comprising:
providing a read and write data buffer at a device end; and
using the read and write data buffer to buffer the read data retrieved from the host memory buffer to answer the host.

Assignees

• Silicon Motion Inc

Inventors

• Huang Chien-Ting
• Chen Liang-Cheng

Classifications

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G06F13/1673 Primary

  using buffers · CPC title

• G06F2212/7205

  Cleaning, compaction, garbage collection, erase control · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title