Digital-to-analog conversion circuit and receiver including the same

Patent metadata

Field	Value
Publication number	US-11700012-B2
Application number	US-202117306421-A
Country	US
Kind code	B2
Filing date	May 3, 2021
Priority date	Nov 11, 2020
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.

First claim

What is claimed is:

1. A digital-to-analog conversion circuit comprising:
a first digital-to-analog converter (DAC) comprising:
a first binary-to-thermometer code converter (BTC) configured to convert a first digital code received through a first input terminal to a first thermometer code;
a plurality of first current cells connected between a first voltage source and a first output node, and configured to provide a first current to the first output node based on the first thermometer code; and
a first current-to-voltage converter directly connected between the first output node and a second voltage source; and

a second DAC comprising:
a second BTC configured to convert a second digital code received through a second input terminal to a second thermometer code;
a plurality of second current cells connected between the first voltage source and the first output node in parallel with the plurality of first current cells, and configured to provide a second current to the first output node based on the second thermometer code; and
a second current-to-voltage converter directly connected between the first output node and the second voltage source in parallel with the first current-to-voltage converter,

wherein the first current-to-voltage converter and the second current-to-voltage converter are configured to convert a sum of the first current and the second current to a first analog voltage corresponding to a weighted sum of the first digital code and the second digital code, and output the first analog voltage at the first output node.

2. The digital-to-analog conversion circuit of claim 1 , wherein, based on the first digital code corresponding to the second digital code,
a magnitude of the first current and a magnitude of the second current have a ratio of c:d, where c and d are positive real numbers,
the first digital code has a ratio of c/(c+d) in a maximum output range of the first analog voltage, and
the second digital code has a ratio of d/(c+d) in the maximum output range of the first analog voltage.

3. The digital-to-analog conversion circuit of claim 1 , wherein:
the first BTC is further configured to generate a first inverted thermometer code which is inversely proportional to the first thermometer code and provide the first inverted thermometer code to the plurality of first current cells,
the plurality of first current cells are further configured to provide a first sub current to a second output node based on the first inverted thermometer code,
the second BTC is further configured to generate a second inverted thermometer code which is inversely proportional to the second thermometer code and provide the second inverted thermometer code to the plurality of second current cells,
the plurality of second current cells are further configured to provide a second sub current to the second output node based on the second inverted thermometer code, and
the first current-to-voltage converter and the second current-to-voltage converter are further configured to convert a sum of the first sub current and the second sub current to a second analog voltage corresponding to a complementary weighted sum of the first digital code and the second digital code, and output the second analog voltage at the second output node.

4. The digital-to-analog conversion circuit of claim 3 ,
wherein the first voltage source provides a power supply voltage and the second voltage source provides a ground voltage,
wherein each of the plurality of first current cells comprises:
a first current source coupled to the power supply voltage, and configured to generate a first base current;
a first transistor including a first source coupled to a first internal node to receive the first base current, a first gate for receiving a bit from among bits of the first thermometer code and a first drain coupled to the first output node; and
a second transistor including a second source coupled to the first internal node to receive the first base current, a second gate for receiving a bit from among bits of the first inverted thermometer code and a second drain coupled to the second output node, and

wherein the first transistor and the second transistor are coupled in parallel with respect to the first internal node.

5. The digital-to-analog conversion circuit of claim 4 ,
wherein each of the plurality of second current cells comprises:
a second current source coupled to the power supply voltage, and configured to generate a second base current;
a third transistor including a third source coupled to a second internal node to receive the second base current, a third gate for receiving a bit from among bits of the second thermometer code and a third drain coupled to the first output node; and
a fourth transistor including a fourth source coupled to the second internal node to receive the second base current, a fourth gate for receiving a bit from among bits of the second inverted thermometer code and a fourth drain coupled to the second output node,

wherein the third transistor and the fourth transistor are coupled in parallel with respect to the second internal node, and
wherein the first base current and the second base current have a ratio of c:d, where c and d are positive real numbers.

6. The digital-to-analog conversion circuit of claim 3 ,
wherein the first voltage source provides a ground voltage and the second voltage source provides a power supply voltage,
wherein each of the plurality of first current cells comprises:
a first current source coupled to the ground voltage, and configured to generate a first base current;
a first transistor including a first source coupled to a first internal node to receive the first base current, a first gate for receiving a bit from among bits of the first thermometer code and a first drain coupled to the first output node; and
a second transistor including a second source coupled to the first internal node to receive the first base current, a second gate for receiving a bit from among bits of the first inverted thermometer code and a second drain coupled to the second output node, and

wherein the first transistor and the second transistor are coupled in parallel with respect to the first internal node.

7. The digital-to-analog conversion circuit of claim 6 ,
wherein each of the plurality of second current cells comprises:
a second current source coupled to the ground voltage, and configured to generate a second base current;
a third transistor including a third source coupled to a second internal node to receive the second base current, a third gate for receiving a bit from among bits of the second thermometer code and a third drain coupled to the first output node; and
a fourth transistor including a fourth source coupled to the second internal node to receive the second base current, a fourth gate for receiving a bit from among bits of the second inverted thermometer code and a second electrode coupled to the second output node,

wherein the third transistor and the fourth transistor are coupled in parallel with respect to the second internal node, and
wherein the first base current and the second base current have a ratio of c:d, where c and d are positive real numbers.

8. The digital-to-analog conversion circuit of claim 3 , wherein, based on the first digital code corresponding to the second digital code,
a magnitude of the first current and a magnitude of the second current have a ratio of c:d, where c and d are positive real numbers,
wherein the first current-to-voltage converter comprises:
a first resistor connected between the first output node and the second voltage source; and
a second resistor connected between the second output node and the second voltage source, and

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Assignees

• Samsung Electronics Co Ltd

Inventors

• Ko Kyeongjoon
• Bae Junhan
• Kim Hanseok
• Park Byeonggyu
• Park Jaehyun
• Song Hobin
• Lee Sooeun

Classifications

• H03M1/742 Primary

  using current sources as quantisation value generators · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M7/165

  Conversion to or from thermometric code · CPC title

• H04B1/16

  Circuits · CPC title

• H03M1/68 Primary

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title