Current steering digital to analog converter

Patent metadata

Field	Value
Publication number	US-10615817-B2
Application number	US-201815895661-A
Country	US
Kind code	B2
Filing date	Feb 13, 2018
Priority date	Nov 7, 2017
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

Digital to analog converter architectures are disclosed that enable the binary scaling of transistor sized to be replaced by transistors of substantially the same size. This significantly reduced the size of the Digital to Analog converter on a wafer. As the currents from the lesser bits of the converter may be very small indeed, some of the transistors are operated in a regime where the gate-source voltage applied to the transistor is below the threshold voltage for the device, the threshold voltage generally being regarded as marking the onset of significant conduction through a field effect transistor.

First claim

The invention claimed is:

1. A digital to analog converter comprising:
a plurality of field effect transistors configured as current generators and arranged in an array, wherein:
a first transistor of the plurality of field effect transistors has a first effective transconductance and outputs a first current by a first terminal of the first transistor of an amount that differs from a second current output by a second terminal of a second transistor of a set of field effect transistors in the plurality of field effect transistors, the second transistor having a second effective transconductance that differs from the first effective transconductance, and
the first and second transistors are operated at sub threshold gate-source voltages, the first terminal being selectively coupled to the second terminal;
a first resistor in a first current path of the set of field effect transistors to establish values of respective currents output by terminals of the set of field effect transistors, the first resistor being coupled via separate resistors to each field effect transistor in the set of field effect transistors, where the terminals of the set of field effect transistors are selectively coupled to the first terminal of the first transistor; and
a second resistor in a second current path of the first transistor and coupled to a third terminal of the first transistor to establish a value of the first current, the first resistor being coupled to the third terminal of the first transistor via the second resistor, the first and second current paths separately coupled to a common supply node, and current flows through the second resistor in the second current path separately from the first resistor in the first current path.

2. A digital to analog converter as claimed in claim 1 , in which the array has a plurality of current outputs, and wherein each output is supplied by a respective current generator formed of a respective field effect transistor, and wherein each transistor is in series with a source voltage modification component or circuit, wherein a resistance value of the first resistor is selected during manufacture of the digital to analog converter based on the second effective transconductance of the second transistor and the first current output by the first transistor.

3. A digital to analog converter as claimed in claim 2 in which the voltage modification components or circuits are arranged in series, with a first voltage modifying component or circuit supplying a modified voltage to a second voltage modifying component or circuit.

4. A digital to analog converter as claimed in claim 3 where the voltage modification components include resistors connected to the source of the respective field effect transistors, the resistors being arranged in a modified R-2R ladder configuration with the resistor ratios differing from an R-2R configuration, and wherein the values of the resistors in the ladder configuration are modified from that of an R-2R ladder configuration to take account of the transconductance of the respective field effect transistors.

5. A digital to analog converter as claimed in claim 1 , further comprising a power supply line, wherein the plurality of field effect transistors of the digital to analog converter correspond to a common digital input, and wherein the first resistor is separate from the power supply line and is coupled between the power supply line and a fourth terminal of the second transistor.

6. A digital to analog converter as claimed in claim 1 in which the first transistor configured as a first current source has a degeneration resistor of value 2R (where R is an arbitrary value), and the second transistor configured as a second current source that outputs the second current half that of the first current output by the first transistor and has a source resistance comprised of a first part that is only in a current flow path to the second transistor and has a value 2R and a second part which is in the current flow path with the second transistor and a further load that draws a current equal to the second current passed by the second transistor and has a value of R+(X 1 −2)R, where X 1 is selected such that the second transistor carries half the first current of the first transistor.

7. A digital to analog converter as claimed in claim 6 , in which X 1 =(ln(2))/gmR)), further comprising a third transistor configured as a third current source that outputs a current half that of the second transistor and has a source resistance comprised of a first part that is only in a current flow path to the third transistor and has a value 2R and a second part which is in the current flow path with the third transistor and a further load that draws a current equal to the current passed by the third transistor and has a value of R+(X2−2)R, wherein X2=(2ln(2))/gmR)).

8. A digital to analog converter as claimed in claim 6 , in which an Nth transistor acting as a Nth current source has a degeneration resistor comprised of a first part that is only in a current flow path to the Nth transistor and has a value 2R and a second part which is in the current flow path with the Nth transistor and a further load that draws a current equal to the current passed by the Nth transistor and has a value of R+(X N −2)R, where X N =(Nln(2))/gmR)).

9. A digital to analog converter as claimed in claim 1 in which each current source has the gate-source voltage of the respective field effect transistor modified by modification device comprising a series connected field effect transistor whose aspect ratio is selected to be between 1.3 and 1.9 times the aspect ratio of the respective field effect transistor acting as a current generator, said selection being made on the basis of a sub-threshold slope factor m associated with the transistors.

10. A digital to analog converter as claimed in claim 9 in which the modification devices comprising respective field effect transistors are arranged in a cascade such that a first modification device supplies current to its respective current generator and to a subsequent modification device, where the output currents from a current generator are in the range of pica-amperes to micro-amperes.

11. A digital to analog converter as claimed in claim 1 in which each current source has the gate-source voltage of the respective field effect transistor modified by modification device comprising a series connected field effect transistor whose aspect ratio is selected to be between 7 and 9.5 times the aspect ratio of the respective field effect transistor acting as a current generator.

12. A digital to analog converter as claimed in claim 1 , wherein the first resistor is an active or passive component which causes the second current to differ from the first current by a specified amount, wherein the first terminal of the first transistor is coupled to a first switch, wherein the second terminal of the second transistor is coupled to a second switch, wherein the first terminal is coupled to the second terminal when the first and second switches direct currents from the first and second terminals to a common given node.

13. A digital to analog converter comprising a plurality of sub-converters acting together to supply a current output, where a first one of the sub-converters comprises an array of transistors whose aspect ratios vary in proportion to the current provided by the respective transistors and one sub-converter comprises at least one DAC array as claimed in claim 1 .

14. A digital to analog converter as claimed in claim 13 , where the digital to analog converter has a second sub-converter comprising an array of transi

Assignees

• Analog Devices Global Unlimited Co

Inventors

• Downey Fergus John

Classifications

• H03M1/745 Primary

  with weighted currents · CPC title

• H03M1/742

  using current sources as quantisation value generators · CPC title

• H03M1/785 Primary

  using resistors, i.e. R-2R ladders · CPC title

• H03M1/78

  using ladder network · CPC title

• H03M1/0612 Primary

  over the full range of the converter, e.g. for correcting differential non-linearity · CPC title