Multi-chip module having a stacked logic chip and memory stack

Patent metadata

Field	Value
Publication number	US-11699681-B2
Application number	US-201916727779-A
Country	US
Kind code	B2
Filing date	Dec 26, 2019
Priority date	Dec 26, 2019
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

An apparatus is formed. The apparatus includes a stack of semiconductor chips. The stack of semiconductor chips includes a logic chip and a memory stack, wherein, the logic chip includes at least one of a GPU and CPU. The apparatus also includes a semiconductor chip substrate. The stack of semiconductor chips are mounted on the semiconductor chip substrate. At least one other logic chip is mounted on the semiconductor chip substrate. The semiconductor chip substrate includes wiring to interconnect the stack of semiconductor chips to the at least one other logic chip.

First claim

The invention claimed is:

1. An apparatus, comprising:
a stack of semiconductor chips, the stack of semiconductor chips comprising a logic chip that is vertically stacked with a memory stack, wherein, the logic chip comprises at least one of a GPU and CPU, the stack of semiconductor chips comprising a first semiconductor chip at a first end of the stack of semiconductor chips and a second semiconductor chip at a second end of the stack of semiconductor chips; and
a semiconductor chip substrate, the stack of semiconductor chips mounted on the semiconductor chip substrate at a first face of the first semiconductor chip, at least one other logic chip mounted on the semiconductor chip substrate, the at least one other logic chip not vertically stacked with the stack of semiconductor chips, the semiconductor chip substrate comprising wiring to interconnect the stack of semiconductor chips to the at least one other logic chip, wherein, electrical power is to be received at a second face of the second semiconductor chip that faces a direction opposite that of the first face of the first semiconductor chip.

2. The apparatus of claim 1 wherein the memory stack is between the semiconductor chip substrate and the logic chip.

3. The apparatus of claim 2 wherein a back of a top memory chip of the memory stack interfaces with a face of the logic chip.

4. The apparatus of claim 3 wherein a substrate of the logic chip comprises a through silicon via.

5. The apparatus of claim 2 wherein a face of a top memory chip of the memory stack interfaces with a face of the logic chip.

6. The apparatus of claim 5 wherein a substrate of the logic chip comprises a through silicon via.

7. The apparatus of claim 2 wherein the electrical power is provided to the logic chip at a top surface of the logic chip.

8. The apparatus of claim 1 wherein the logic chip is between the semiconductor chip substrate and the memory stack.

9. The apparatus of claim 8 wherein a back of the logic chip interfaces with a face of a bottom memory chip of the memory stack.

10. The apparatus of claim 9 wherein a substrate of the bottom memory chip of the memory stack comprises a through silicon via.

11. The apparatus of claim 8 wherein a face of the logic chip interfaces with a face of a bottom memory chip of the memory stack.

12. The apparatus of claim 11 wherein a substrate of the bottom memory chip of the memory stack comprises a through silicon via.

13. The apparatus of claim 8 wherein the electrical power is provided to the memory stack at a top surface of the memory stack.

14. A computing system, comprising:
a networking interface;
non volatile mass storage; and
a multi-chip module comprising a) and b) below:
a) a stack of semiconductor chips, the stack of semiconductor chips comprising a logic chip that is vertically stacked with a memory stack, wherein, the logic chip comprises at least one of a GPU and CPU, the stack of semiconductor chips comprising a first semiconductor chip at a first end of the stack of semiconductor chips and a second semiconductor chip at a second end of the stack of semiconductor chips; and
b) a semiconductor chip substrate, the stack of semiconductor chips mounted on the semiconductor chip substrate at a first face of the first semiconductor chip, at least one other logic chip mounted on the semiconductor chip substrate, the at least one other logic chip not vertically stacked with the stack of semiconductor chips, the semiconductor chip substrate comprising wiring to interconnect the stack of semiconductor chips to the at least one other logic chip, wherein, electrical power is to be received at a second face of the second semiconductor chip that faces a direction opposite that of the first face of the first semiconductor chip.

15. The computing system of claim 14 wherein the memory stack is between the semiconductor chip substrate and the logic chip.

16. The computing system of claim 15 wherein the electrical power is provided to the logic chip at a top surface of the logic chip.

17. The computing system of claim 15 wherein second electrical power is provided to at least one of the memory stack and the logic chip through the semiconductor chip substrate.

18. The computing system of claim 14 wherein the logic chip is between the semiconductor chip substrate and the memory stack.

19. The computing system of claim 18 wherein the electrical power is provided to the memory stack at a top surface of the memory stack.

20. A method, comprising:
stacking multiple memory chip wafers and a logic chip wafer;
dicing the stacked memory chip wafers and logic chip wafer to form a logic chip that is vertically stacked with a memory chip stack;
mounting the stacked logic chip and memory chip stack on a semiconductor chip substrate;
mounting at least one other logic chip to the semiconductor chip substrate such that the at least one other logic chip is not vertically stacked with the stacked logic chip and memory chip stack; and,
connecting a power connection to a first end of the stacked logic chip and memory chip stack that is opposite a second end of the stacked logic chip and memory chip stack where the stacked logic chip and memory chip stack are mounted to the semiconductor chip substrate.

Assignees

• Intel Corp

Inventors

• Sharma Abhishek
• Yoo Hui Jae
• Le Van H
• Sumbul Huseyin Ekin
• Knag Phil
• Chen Gregory K
• Krishnamurthy Ram

Classifications

• H01L2224/32225

  Electricity · mapped topic

• H01L25/0657 Primary

  Electricity · mapped topic

• H01L2224/32145

  Electricity · mapped topic

• G11C11/407

  for memory cells of the field-effect type · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title