Analog in-memory computing based inference accelerator

Patent metadata

Field	Value
Publication number	US-11699482-B2
Application number	US-202117447131-A
Country	US
Kind code	B2
Filing date	Sep 8, 2021
Priority date	Sep 9, 2020
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

A compute cell for in-memory multiplication of a digital data input and a balanced ternary weight, and an in-memory computing device including an array of the compute cells, are provided. In one aspect, the compute cell includes a set of input connectors for receiving modulated input signals representative of a sign and a magnitude of the data input, and a memory unit configured to store the ternary weight. A logic unit connected to the set of input connectors and the memory unit receives the data input and the ternary weight. The logic unit selectively enables one of a plurality of conductive paths for supplying a partial charge to a read bit line during a compound duty cycle of the set of input signals as a function of the respective signs of data input and ternary weight, and disables each of the plurality of conductive paths if at least one of the ternary weight and data input have zero magnitude.

First claim

What is claimed is:

1. A compute cell for in-memory multiplication of a digital data input and a balanced ternary weight, comprising:
a set of input connectors for receiving a corresponding set of modulated input signals (A+, A−) representative of a sign and a magnitude of the digital data input;
a memory unit configured for storing the balanced ternary weight;
a logic unit connected to the set of input connectors and the memory unit to receive the data input and the balanced ternary weight, the logic unit configured to: selectively enable one of a plurality of conductive paths for supplying a first charge to a read bit line (S; S+, S−) during a duty cycle of the set of input signals if the data input and the balanced ternary weight both have a positive sign or both have a negative sign, selectively enable a different one of the plurality of conductive paths for supplying a second charge to the same one read bit line (S), or to a different one read bit line (S+, S−), during the duty cycle if the data input and the balanced ternary weight have opposite signs, and disable each of the plurality of conductive paths if at least one of the group consisting of the balanced ternary weight and the data input has zero magnitude, in order to prevent any supply of charges to the one or more read bit lines, wherein the duty cycle is indicative of the data input magnitude, and wherein a ratio of the first to the second charge is negative one if the first and second charge are supplied to a same read bit line, and positive one if the first and second charge are supplied to different read bit lines; and
at least one current source, each current source being disposed in a conductive path of the plurality of conductive paths and configured to supply one of the first and second charge by inducing a constant current on that conductive path during the duty cycle.

2. The compute cell according to claim 1 , wherein the memory unit comprises a first storage cell and a second storage cell for storing two binary-valued weight signals (W+, W−) encoding the balanced ternary weight, and wherein at least one of the first storage cell and second storage cell comprises one of the group consisting of: SRAM cell, DRAM cell, Ferro-FET, flash transistor, resistive RAM, phase-change memory.

3. The compute cell according to claim 1 , wherein the set of input connectors comprises a first and a second single-ended input connector for receiving a modulated first and second input signal (/A+, /A−), and wherein the logic unit further comprises:
a first and a second output (OUT+, OUT−) connectable to respective ones of a differential pair of read bit lines (S+, S−);
a first transistor connected between the first output (OUT+) and the first input connector and having a gate electrode connected to the memory unit to receive a first one (W+) of a set of binary-valued weight signals encoding the balanced ternary weight, for selectively enabling a first conductive path if the data input and the balanced ternary weight both have positive sign;
a second transistor connected between the first output and the second input connector and having a gate electrode connected to the memory unit to receive a second one (W−) of the set of binary-valued weight signals encoding the balanced ternary weight, for selectively enabling a second conductive path if the data input and the balanced ternary weight both have negative sign;
a third transistor connected between the second output (OUT−) and the first input connector and having a gate electrode connected to the memory unit to receive the second binary-valued weight signal (W−), for selectively enabling a third conductive path if the data input has positive sign and the balanced ternary weight has negative sign; and
a fourth transistor connected between the second output (OUT−) and the second input connector and having a gate electrode connected to the memory unit to receive the first binary-valued weight signal (W+), for selectively enabling a fourth conductive path if the data input has negative sign and the balanced ternary weight has positive sign.

4. The compute cell according to claim 3 , wherein transistors with gate electrodes connected to the memory unit are provided as long-channel transistors.

5. The compute cell according to claim 1 , wherein the set of input connectors comprises a first and a second single-ended input connector for receiving a modulated first and second input signal (A+, /A−), and wherein the logic unit further comprises:
a first and a second output (OUT+, OUT−) connectable to respective ones of a differential pair of read bit lines (S+, S−);
a first transistor of a first conductivity type connected between the first output (OUT+) and the first input connector and having a gate electrode connected to the memory unit to receive a first one (/W+) of a set of binary-valued weight signals encoding the balanced ternary weight, for selectively enabling a first conductive path if the data input and the balanced ternary weight both have positive sign;
a second transistor of a second conductivity type, opposite to the first conductivity type, connected between the first output (OUT+) and the second input connector and having a gate electrode connected to the memory unit to receive the complement (W+) of the first binary-valued weight signal, for selectively enabling a second conductive path if the data input has negative sign and the balanced ternary weight has positive sign;
a third transistor of the first conductivity type connected between the second output (OUT−) and the first input connector and having a gate electrode connected to the memory unit to receive a second one (/W−) of the set of binary-valued weight signals encoding the balanced ternary weight, for selectively enabling a third conductive path if the data input has positive sign and the balanced ternary weight has negative sign; and
a fourth transistor of the first conductivity type connected between the second output (OUT−) and the second input connector and having a gate electrode connected to the memory unit to receive the complement (W−) of the first binary-valued weight signal, for selectively enabling a fourth conductive path if the data input and the balanced ternary weight both have positive sign.

6. The compute cell according to claim 1 , wherein the set of input connectors comprises a first and a second single-ended input connector for receiving a modulated first and second input signal (A+, A−), and wherein the logic unit further comprises:
a first and a second output (OUT+, OUT−) connectable to respective ones of a differential pair of read bit lines (S+, S−);
a first pair of drain-source connected transistors connected between the first output (OUT+) and a logic power supply, for selectively enabling a first conductive path if the data input and the balanced ternary weight both have positive sign, wherein a first transistor of the first transistor pair has a gate electrode connected to the memory unit to receive a first one (W+) of a set of binary-valued weight signals encoding the balanced ternary weight, and a second transistor of the first transistor pair has a gate electrode connected to the first input connector;
a second pair of drain-source connected transistors connected between the first output (OUT+) and a logic power supply, for selectively enabling a second conductive path if the data input and the balanced ternary weight both have negative sign, wherein a first transistor of the second transistor pair has a gate electrode connected to the memory unit to receive a second one (W−) of a set of binary-valued weight signals encoding the balanced ternary weight, and a second transistor of the second transistor pair has a gate electrode connected to the second input connector;
a third pair of drain-sou

Assignees

• Imec Vzw

Inventors

• Cosemans Stefan
• Papistas Ioannis
• Debacker Peter

Classifications

• G06J1/00 Primary

  Hybrid computing arrangements · CPC title

• G06F17/16

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G06N20/00

  Machine learning · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title