Scalable, hierarchical power delivery system

Patent metadata

Field	Value
Publication number	US-11698669-B2
Application number	US-202117412230-A
Country	US
Kind code	B2
Filing date	Aug 25, 2021
Priority date	Aug 25, 2021
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

A hierarchical, scalable power delivery system is disclosed. The power delivery system includes a first level of power converter circuitry configured to generate one or more first level regulated supply voltages, and a second level of power converter circuitry configured to generate one or more second level regulated supply voltages. The first level of power converter circuitry receives an input supply voltage, while the second level power converter circuitry receives the one or more first level supply voltages. The second level power converter circuitry is configured to provide the second level regulated supply voltages to a computing element configured to operate as a single, logical computer system, the computing element being configured to operate in a number of power configurations having differing numbers of load circuits. Different portions of the hierarchical power delivery system may be selectively enabled for corresponding ones of the power configurations of the computing element.

First claim

What is claimed is:

1. An apparatus, comprising:
a hierarchical power delivery circuit that includes:
a first level of power converter circuitry that is configured to generate, from an input voltage, a plurality of first-level regulated supply voltages; and
a second level of power converter circuitry that is configured to generate, from corresponding ones of the plurality of first-level regulated supply voltages, a plurality of second-level regulated supply voltages to a computing element comprising one or more integrated circuits configured to operate as a single, logical computer system, wherein the computing element is configured to operate in a plurality of power configurations having differing numbers of load circuits; and
wherein the hierarchical power delivery circuit is configured to selectively enable differing portions of the first and second levels of power converter circuitry for corresponding ones of the plurality of power configurations of the computing element.

2. The apparatus of claim 1 , wherein the plurality of first-level regulated supply voltages includes a first regulated supply voltage and a second regulated supply voltage generated by a first power converter and a second power converter, respectively.

3. The apparatus of claim 2 , wherein the plurality of second-level regulated supply voltages includes a third regulated supply voltage and a fourth regulated supply voltage, wherein ones of a first plurality of power converters implemented on a first integrated circuit are configured to generate the third regulated supply voltage, and wherein ones of a second plurality of power converters implemented on a second integrated circuit are configured to generate the fourth regulated supply voltage.

4. The apparatus of claim 1 , wherein the second level of power converter circuitry includes a plurality of power converters, wherein a number of enabled ones of the plurality of power converters is dependent on a particular one of the plurality of power configurations of the computing element.

5. The apparatus of claim 1 , wherein the second level of power converter circuitry includes a plurality of power converters, wherein a number of enabled ones of the plurality of power converters is dependent on a number of integrated circuits comprising the computing element.

6. The apparatus of claim 1 , wherein the first level of power converter circuitry includes at least one multi-phase power converter, wherein a number of enabled phases of the at least one multi-phase power converter is dependent on a number of load circuits supplied to the one or more integrated circuits of the computing element by the second level of power converter circuitry.

7. The apparatus of claim 1 , wherein the second level of power converter circuitry includes a power converter having control circuitry configured to control power-up and power down sequences for at least one power converter of the first level of power converter circuitry and one or more power converters of the second level of power converter circuitry.

8. The apparatus of claim 1 , wherein the second level of power converter circuitry includes one or more coupled-inductor buck converters.

9. The apparatus of claim 1 , further comprising at least one control bus coupled between respective power converters of the first and second levels of power converter circuitry.

10. The apparatus of claim 1 , wherein the first level of power converter circuitry includes at least one power converter configured to remain operating when the input voltage is present, and wherein the first and second levels of power converter circuitry further include respective power converters configured to enter a sleep mode.

11. A system comprising:
a computing element comprised of one or more integrated circuits configured to operate as a single, logical computer system, wherein the computing element is configured to operate in a plurality of power configurations having differing numbers of load circuits; and
a power delivery system configured to provide power to the computing element, wherein the power delivery system comprises:
a first power converter level comprising first and second power converters configured to generate, from a common input voltage, first and second regulated supply voltages; and
a second power converter level comprising a first plurality of power converters and a second plurality of power converters, wherein ones of the first plurality of power converters are configured to generate, from the first regulated supply voltage, a third regulated supply voltage, and wherein ones of the second plurality of power converters are configured to generate, from the second regulated supply voltage, a fourth regulated supply voltage;
wherein the power delivery system is configured to selectively enable differing portions of the first and second power converter levels for corresponding ones of the plurality of power configurations of the computing element.

12. The system of claim 11 , wherein the computing element comprises a computing architecture that is scalable from a first one of the plurality of power configurations comprising a single integrated circuit die to one or more additional ones of the plurality of power configurations comprising two or more integrated circuit dies, wherein the two or more integrated circuit dies are configured as a single system in which existence of multiple integrated circuit dies is transparent to software executing on the single system.

13. The system of claim 11 , wherein the plurality of power configurations includes at least one configuration wherein a portion of a single integrated circuit is disabled.

14. The system of claim 11 , wherein the first and second power converters are multi-phase power converters, wherein a number of phases enabled for ones of the first and second power converters is dependent on a selected one of the plurality of power configurations.

15. The system of claim 11 , wherein a number of enabled ones of the first plurality of power converters and a number of enabled ones of the second plurality of power converters is dependent on a selected one of the plurality of power configurations.

16. The system of claim 11 , wherein the first plurality of power converters comprises a plurality of coupled-inductor buck converters.

17. The system of claim 11 , wherein the second power converter level includes a power converter having control circuitry configured to control, via a control bus, a power-up sequence for at least one power converter of the first power converter level and one or more power converters of the second power converter level.

18. A non-transitory computer readable medium storing instructions that, when executed on a computer system, are usable to manufacture an electronic circuit, the electronic circuit comprising:
a hierarchical power delivery circuit that includes:
a first level of power converter circuitry that is configured to generate, from an input voltage, a first supply voltage and a second supply voltage;
a second level of power converter circuitry that is configured to generate, from corresponding ones of the first and second supply voltages, one or more instances of a third supply voltage and one or more instances of a fourth supply voltage to be provided to a computing element comprising one or more integrated circuits configured to operate as a single, logical computer system, wherein the computing element is configured to operate in a plurality of power configurations having differing numbers of load circuits; and

wherein the hierarchical powe

Assignees

• Apple Inc

Inventors

• Cox Keith
• Langlinais Jamie L
• Sodhi Inder M

Classifications

• G06F1/263 Primary

  Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence) · CPC title

• H02M1/007

  Plural converter units in cascade (push-pull DC/DC converters with pre-regulator H02M3/3374; DC-AC converters following a DC-DC stage including a high frequency transformer H02M7/4807; DC-AC converters following a DC-DC conversion stage generating periodically varying voltages H02M7/4826) · CPC title

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• H02M3/155

  using semiconductor devices only · CPC title

• H02M1/0067

  Converter structures employing plural converter units, other than for parallel operation of the units on a single load · CPC title