Core layer with fully encapsulated co-axial magnetic material around PTH in IC package substrate

Patent metadata

Field	Value
Publication number	US-11696407-B2
Application number	US-202117560004-A
Country	US
Kind code	B2
Filing date	Dec 22, 2021
Priority date	Mar 2, 2018
Publication date	Jul 4, 2023
Grant date	Jul 4, 2023

Abstract

Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

First claim

What is claimed is:

1. A method of forming an inductor, comprising:
forming a first opening through a substrate core;
filling the first opening with a magnetic material;
forming a second opening through the magnetic material to define a magnetic sheath;
disposing a plugging layer comprising a dielectric material into the second opening;
disposing a first layer comprising a dielectric material over a first surface of the magnetic sheath;
disposing a second layer comprising a dielectric material over a second surface of the magnetic sheath;
forming a third opening through the plugging layer, wherein surfaces of the magnetic sheath are separated from the third opening by the plugging layer; and
disposing conductive layers over sidewalls of the third opening to form a conductive through via.

2. The method of claim 1 , wherein a first surface of the magnetic sheath is substantially coplanar with a first surface of the substrate core, and wherein a second surface of the magnetic sheath is substantially coplanar with a second surface of the substrate core.

3. The method of claim 2 , wherein the magnetic sheath is fully embedded by the substrate core, the plugging layer, the first layer comprising a dielectric material, and the second layer comprising a dielectric material.

4. The method of claim 1 , wherein one or more of the first opening, the second opening, and the third opening are formed with a mechanical drilling process.

5. The method of claim 4 , wherein one or more of the first opening, the second opening, and the third opening are formed with a laser drilling process.

6. The method of claim 1 , wherein a diameter of the third opening is equal to a diameter of a plated through-hole via formed through the substrate core in a non-inductor region.

7. The method of claim 1 , further comprising: disposing a second plugging layer comprising a dielectric material into the third opening.

8. The method of claim 7 , wherein the plugging layer and the second plugging layer comprise the same dielectric material.

9. The method of claim 1 , wherein the third opening is formed through the first layer comprising a dielectric material and the second layer comprising a dielectric material.

10. The method of claim 1 , wherein a thickness of the plugging layer separating the magnetic sheath from the conductive through via is 50 μm or less, and wherein a thickness of the magnetic sheath is 50 μm or greater.

11. The method of claim 1 , wherein a permeability of the magnetic sheath is greater than 20.

12. A method of fabricating an inductor, the method comprising:
forming a substrate core;
forming a conductive through-hole through the substrate core;
forming a magnetic sheath around the conductive through-hole, wherein the magnetic sheath is separated from the conductive through-hole by a first plugging layer comprising a dielectric material; and
forming a second plugging layer filling the conductive through-hole, wherein the second plugging layer comprises a dielectric material.

13. The method of claim 12 , wherein a first surface of the magnetic sheath is substantially coplanar with a first surface of the substrate core and wherein a second surface of the magnetic sheath is substantially coplanar with a second surface of the substrate core.

14. The method of claim 13 , wherein a first layer comprising a dielectric material is in contact with the first surface of the magnetic sheath, and wherein a second layer comprising a dielectric material is in contact with the second surface of the magnetic sheath.

15. The method of claim 14 , wherein the magnetic sheath is fully embedded.

16. The method of claim 12 , wherein a thickness of the first plugging layer separating the magnetic sheath from the conductive through-hole is 50 microns or less.

17. The method of claim 12 , wherein a thickness of the magnetic sheath is 50 microns or greater.

18. The method of claim 12 , wherein a diameter of the conductive through-hole is the same diameter as conductive through vias disposed in non-inductor regions of the substrate core.

19. The method of claim 12 , wherein a permeability of the magnetic sheath is greater than 10.

20. The method of claim 19 , wherein the permeability of the magnetic sheath is greater than 20.

21. The method of claim 12 , wherein the second plugging layer is the same material as the first plugging layer separating the magnetic sheath from the conductive through-hole.

Assignees

• Intel Corp

Inventors

• Zhang Chong
• Wang Ying
• Zhao Junnan
• Xu Cheng
• Deng Yikang

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/635

  Through-vias · CPC title