Active matrix substrate and method of manufacturing same

Patent metadata

Field	Value
Publication number	US-11069722-B2
Application number	US-201816617573-A
Country	US
Kind code	B2
Filing date	May 21, 2018
Priority date	May 31, 2017
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

An active matrix substrate according to an embodiment of the present invention includes: a substrate; a plurality of first TFTs supported by the substrate and provided in a non-displaying region; and a peripheral circuit including the plurality of first TFTs. Each first TFT includes: a first gate electrode provided on the substrate; a first gate insulating layer covering the first gate electrode; a first oxide semiconductor layer opposed to the first gate electrode via the first gate insulating layer; and a first source electrode and a first drain electrode connected to a source contact region and a drain contact region of the first oxide semiconductor layer. Each first TFT has a bottom contact structure. A first region of the first gate insulating layer that overlaps the channel region has a thickness which is smaller than a thickness of a second region of the first gate insulating layer that overlaps the source contact region and the drain contact region.

First claim

The invention claimed is:

1. An active matrix substrate having a displaying region including a plurality of pixels and a non-displaying region located around the displaying region, the active matrix substrate comprising:
a substrate;
a plurality of first TFTs supported by the substrate and provided in the non-displaying region;
a peripheral circuit including the plurality of first TFTs; and
a plurality of second TFTs supported by the substrate and provided in the displaying region and/or the non-displaying region; wherein
each of the plurality of first TFTs includes:
a first gate electrode provided on the substrate;
a first gate insulating layer covering the first gate electrode;
a first oxide semiconductor layer opposed to the first gate electrode via the first gate insulating layer, the first oxide semiconductor layer including a channel region and a source contact region and a drain contact region located on opposite sides of the channel region;
a first source electrode connected to the source contact region of the first oxide semiconductor layer; and
a first drain electrode connected to the drain contact region of the first oxide semiconductor layer;

each of the plurality of first TFTs includes a bottom contact structure such that the first source electrode and the first drain electrode are in contact with a lower face of the first oxide semiconductor layer;
a first region of the first gate insulating layer that overlaps the channel region has a thickness which is smaller than a thickness of a second region of the first gate insulating layer that overlaps the source contact region and the drain contact region;
each of the plurality of second TFTs includes:
a second gate electrode provided on the substrate;
a second gate insulating layer covering the second gate electrode;
a second oxide semiconductor layer opposed to the second gate electrode via the second gate insulating layer, the second oxide semiconductor layer including a channel region and a source contact region and a drain contact region located on opposite sides of the channel region of the second oxide semiconductor layer;
a second source electrode connected to the source contact region of the second oxide semiconductor layer; and
a second drain electrode connected to the drain contact region of the second oxide semiconductor layer;

each of the plurality of second TFTs has a top contact structure such that the second source electrode and the second drain electrode are in contact with an upper face of the second oxide semiconductor layer; and
a third oxide semiconductor layer which covers the channel region of the second oxide semiconductor layer is provided the third oxide semiconductor layer is in a same layer as the first oxide semiconductor layer.

2. The active matrix substrate of claim 1 , wherein the peripheral circuit is a demultiplexer circuit.

3. The active matrix substrate of claim 1 , wherein a thickness of the first region of the first gate insulating layer is set so that a gate capacitance of each of the plurality of first TFTs is equal to or greater than twice a gate capacitance of each of the plurality of second TFTs.

4. The active matrix substrate of claim 1 , wherein the plurality of second TFTs include a pixel TFT disposed for each of the plurality of pixels.

5. The active matrix substrate of claim 1 , further comprising a driving circuit provided in the non-displaying region, wherein
the plurality of second TFTs include a TFT composing the driving circuit.

6. The active matrix substrate of claim 1 , wherein the second oxide semiconductor layer has a multilayer structure.

7. The active matrix substrate of claim 1 , wherein the first oxide semiconductor layer comprises an In—Ga—Zn—O based semiconductor.

8. The active matrix substrate of claim 7 , wherein the In—Ga—Zn—O based semiconductor includes a crystalline portion.

9. A method of producing an active matrix substrate having a displaying region including a plurality of pixels and a non-displaying region located around the displaying region, the active matrix substrate comprising:
a substrate;
a plurality of first TFTs supported by the substrate and provided in the non-displaying region; and
a peripheral circuit including the plurality of first TFTs,
each of the plurality of first TFTs including:
a first gate electrode provided on the substrate;
a first gate insulating layer covering the first gate electrode;
a first oxide semiconductor layer opposed to the first gate electrode via the first gate insulating layer, the first oxide semiconductor layer including a channel region and a source contact region and a drain contact region located on opposite sides of the channel region;
a first source electrode connected to the source contact region of the first oxide semiconductor layer; and
a first drain electrode connected to the drain contact region of the first oxide semiconductor layer,
the method comprising:
(A) a step of forming the first gate electrode on the substrate;
(B) a step of forming the first gate insulating layer covering the first gate electrode;
(C) a step of forming the first source electrode and the first drain electrode on the first gate insulating layer;
(D) a step of forming the first oxide semiconductor layer after step (C), wherein the first oxide semiconductor layer is formed so that the first source electrode and the first drain electrode are in contact with a lower face of the first oxide semiconductor layer; and
(E) a step, between step (C) and step (D), of causing a first region of the first gate insulating layer that is exposed between the first source electrode and the first drain electrode to become thinner than a second region of the first gate insulating layer that overlaps the first source electrode and the first drain electrode; wherein
the active matrix substrate further includes a plurality of second TFTs supported by the substrate and provided in the displaying region and/or the non-displaying region,
each of the plurality of second TFTs including:
a second gate electrode provided on the substrate;
a second gate insulating layer covering the second gate electrode;
a second oxide semiconductor layer opposed to the second gate electrode via the second gate insulating layer, the second oxide semiconductor layer including a channel region and a source contact region and a drain contact region located on opposite sides of the channel region of the second oxide semiconductor layer;
a second source electrode connected to the sourc contact region of the second oxide semiconductor layer; and
a second drain electrode connected to the drain contact region of the second oxide semiconductor layer,

the method further comprising a step (G), between step (B) and step (C), of forming the second oxide semiconductor layer on the second gate insulating layer; and
in step (C), when the first source electrode and the first drain electrode are formed, the second source electrode and the second drain electrode are formed so as to be in contact with an upper face of the second oxide semiconductor layer.

10. The method of producing an active matrix substrate of claim 9 , wherein the peripheral circuit is a demultiplexer circuit.

11. The method of producing an active matrix substrate of claim 9 , wherein, in step (E), the first region of the first gate insulating layer is made thin so that a gate capacitance of each of the plurality of first TFTs is equal to or greater than twice that of a case where step (E) is not performed.

12. The method of producing an active matrix substrate of claim 9 , wherein,
step (B) comprises:
(B1) a step of forming a silicon nitride layer cove

Assignees

• Sharp Kk

Inventors

• Matsukizono Hiroshi

Classifications

• H10D86/021

  of multiple TFTs · CPC title

• H10D84/0126

  the components including insulated gates, e.g. IGFETs · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title