Monolithic integrated quantum dot photonic integrated circuits

US11693178B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11693178-B2
Application numberUS-202217882909-A
CountryUS
Kind codeB2
Filing dateAug 8, 2022
Priority dateMay 24, 2018
Publication dateJul 4, 2023
Grant dateJul 4, 2023

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A photonic integrated circuit (PIC) includes a semiconductor substrate, one or more passive components, and one or more active components. The one or more passive components are fabricated on the semiconductor substrate, wherein the passive components are fabricated in a III-V type semiconductor layer. The one or more active components are fabricated on top of the one or more passive components, wherein optical signals are communicated between the one or more active components via the one or more passive components.

First claim

Opening claim text (preview).

The invention claimed is: 1. A photonic integrated circuit (PIC) comprising: a semiconductor substrate; a first III-V type semiconductor layer located vertically adjacent to the semiconductor substrate; one or more passive components fabricated in the first III-V type semiconductor layer; a first active component located adjacent the one or more passive components fabricated in the first III-V type semiconductor layer; and a second active component located adjacent the one or more passive components fabricated in the first III-V type semiconductor layer, wherein the first active component and second active component are fabricated in a second III-V type semiconductor layer located vertically adjacent to the first III-V semiconductor layer and wherein at least one of the first active component and/or the second active component includes one or more active layers comprised of quantum dots (QDs), wherein optical signals are communicated by the one or more passive components from the first active component to the second active component wherein at least one of the first active component or the second active component includes one or more active layers comprised of quantum wells (QWs). 2. The PIC of claim 1 , wherein the first active component includes one or more active layers comprised of QDs and the second active component includes one or more layers comprised of quantum wells (QWs). 3. The PIC of claim 2 , wherein the second active component is a QW modulator and the one or more active layers associated with a QW modulator includes modulator material regrown to increase a bandgap of the active layer of the QW modulator relative to a bandgap of the QD layers in the first active component. 4. The PIC of claim 2 , wherein the first active components include one or more of a QD laser and a QD semiconductor optical amplifier (SOA) and wherein the second active components include one or more of a QW modulator and a QW photodetector. 5. The PIC of claim 1 , wherein the one or more active layers associated with the first active component and/or the second active component includes a plurality of vertically stacked layers of QDs separated by p-doped regions. 6. The PIC of claim 1 , wherein the one or more active layers associated with the first active component and/or one or more active layers associated with the second active component include intermixed QDs. 7. The PIC of claim 6 , wherein the intermixed QDs includes intermixing between the QD composition and surrounding barrier layers. 8. The PIC of claim 1 , wherein a planar surface of the semiconductor substrate, a buffer layer located between the semiconductor substrate and the first III-V semiconductor layer, and/or the first III-V semiconductor layer associated with the first active component and/or the second active component is patterned to vary a size of the QDs formed in the one or more active layers located adjacent the patterned planar surface. 9. The PIC of claim 8 , wherein the pattern provided on the planar surface of the semiconductor substrate, the buffer layer, and/or the first III-V semiconductor layer includes etches having a depth x, wherein each etch is separated from adjacent etches by a distance y. 10. The PIC of claim 9 , wherein the first active component is a QD laser and the second active component is a quantum well (QW) modulator. 11. The PIC of claim 10 , wherein the QW modulator includes a first waveguide interferometer arm, a second waveguide interferometer arm, a first top contact associated with the first waveguide interferometer arm and a second top contact associated with the second waveguide interferometer arm. 12. A method of fabricating a monolithically integrated photonic integrated circuit (PIC), the method comprising: epitaxially depositing at least first and second III-V semiconductor layers on a semiconductor substrate, wherein the first III-V semiconductor layer is located vertically adjacent to the semiconductor substrate; and processing the first III-V semiconductor layers to fabricate passive components and processing the second III-V semiconductor layers to fabricate two or more active components, wherein at least one of the two or more active components are comprised of active regions that include quantum dot (QD) layers, wherein the QD layers are located vertically adjacent to the first III-V semiconductor layers and wherein the active components are optically coupled to one another via the passive components, wherein at least one of the two or more active components are comprised of active regions that include quantum wells (QW) layers, wherein the QW layers are located vertically adjacent to the first III-V semiconductor layers. 13. The method of claim 12 , further including: selectively intermixing the QD layer with adjacent III-V layers in areas corresponding with one or more active components to modify the bandgap associated with the intermixed QD layer. 14. The method of claim 12 , further including: patterning a planar surface associated with the semiconductor substrate in a region associated with either the first active optical component or the second active optical component prior to epitaxially depositing the III-V semiconductor layers. 15. The method of claim 12 , wherein processing the second III-V semiconductor layers to fabricate two or more active components includes fabricating a first active component comprised of active regions that include quantum dot (QD) layers and a second active component comprised of active regions that include quantum well (QW) layers. 16. The method of claim 15 , wherein the second active component is a QW modulator and the one or more active layers associated with a QW modulator includes modulator material regrown to increase a bandgap of the active layer of the QW modulator relative to a bandgap of the QD layers in the first active component. 17. The method of claim 16 , wherein the first active components include one or more of a QD laser and a QD semiconductor optical amplifier (SOA) and wherein the second active components include one or more of a QW modulator and a QW photodetector.

Assignees

Inventors

Classifications

  • Combinations of two or more optical elements · CPC title

  • Integrated optical circuits characterised by the manufacturing method · CPC title

  • comprising photonic band-gap structures or photonic lattices · CPC title

  • Nanooptics, e.g. quantum optics or photonic crystals · CPC title

  • H01S5/021Primary

    Silicon based substrates · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11693178B2 cover?
A photonic integrated circuit (PIC) includes a semiconductor substrate, one or more passive components, and one or more active components. The one or more passive components are fabricated on the semiconductor substrate, wherein the passive components are fabricated in a III-V type semiconductor layer. The one or more active components are fabricated on top of the one or more passive components…
Who is the assignee on this patent?
Univ California
What technology area does this patent fall under?
Primary CPC classification G02B6/12004. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 04 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).