Monolithic integrated quantum dot photonic integrated circuits

Patent metadata

Field	Value
Publication number	US-11435524-B2
Application number	US-201917058057-A
Country	US
Kind code	B2
Filing date	May 24, 2019
Priority date	May 24, 2018
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

A photonic integrated circuit (PIC) includes a semiconductor substrate, one or more passive components, and one or more active components. The one or more passive components are fabricated on the semiconductor substrate, wherein the passive components are fabricated in a III-V type semiconductor layer. The one or more active components are fabricated on top of the one or more passive components, wherein optical signals are communicated between the one or more active components via the one or more passive components.

First claim

The invention claimed is:

1. A photonic integrated circuit (PIC) comprising:
a semiconductor substrate;
a first III-V type semiconductor layer located vertically adjacent to the semiconductor substrate;
one or more passive components fabricated in the first III-V type semiconductor layer;
a first active component located adjacent the one or more passive components fabricated in the first III-V type semiconductor layer, the first active component having one or more active layers comprised of first quantum dots (QDs); and
a second active component located adjacent the one or more passive components fabricated in the first III-V type semiconductor layer, the second active component having one or more active layers comprised of second quantum dots (QDs), wherein the first active component and second active component are fabricated in a second III-V type semiconductor layer located vertically adjacent to the first III-V semiconductor layer and wherein optical signals are communicated by the one or more passive components from the first active component to the second active component.

2. The PIC of claim 1 , wherein the one or more active layers associated with the first active component and/or the second active component includes a plurality of vertically stacked layers of QDs separated by p-doped regions.

3. The PIC of claim 1 , wherein the one or more active layers associated with the first active component is comprised of QDs having a first size and the one or more active layers associated with the second active component is comprised of QDs having a second size.

4. The PIC of claim 1 , wherein the one or more active layers associated with the first active component and/or one or more active layers associated with the second active component include intermixed QDs.

5. The PIC of claim 4 , wherein the intermixed QDs includes intermixing between the QD composition and surrounding barrier layers.

6. The PIC of claim 1 , wherein a planar surface of the semiconductor substrate, a buffer layer located between the silicon semiconductor substrate and the first III-V semiconductor layer, and/or the first III-V semiconductor layer and which is associated with the first active component and/or the second active component is patterned to vary a size of the QDs formed in the one or more active layers located adjacent the patterned planar surface.

7. The PIC of claim 6 , wherein the pattern provided on the planar surface of the semiconductor substrate, the buffer layer, and/or the first III-V semiconductor layer includes etches having a depth x, wherein each etch is separated from adjacent etches by a distance y.

8. The PIC of claim 1 , wherein the second active component is a QD modulator and the one or more active layers associated with a QD modulator includes modulator material regrown with quantum dots that differ in size, composition, or surrounding material from the one or more active layers associated with the first active component to increase the bandgap of the active layer of the QD modulator.

9. The PIC of claim 1 , wherein the first and second active components include one or more of a QD laser, a QD modulator, a QD semiconductor optical amplifier (SOA), and a QD photodetector.

10. The PIC of claim 9 , wherein the first active component is a QD laser and the second active component is a QD modulator.

11. The PIC of claim 10 , wherein the QD modulator includes a first waveguide interferometer arm, a second waveguide interferometer arm, a first top contact associated with the first waveguide interferometer arm and a second top contact associated with the second waveguide interferometer arm.

12. A method of fabricating a monolithically integrated photonic integrated circuit (PIC), the method comprising:
epitaxially depositing at least first and second III-V semiconductor layers on a semiconductor substrate, wherein the first III-V semiconductor layer is located vertically adjacent to the semiconductor substrate; and
processing the first III-V semiconductor layers to fabricate passive components and processing the second III-V semiconductor layers to fabricate two or more active components comprised of active regions that include quantum dot (QD) layers, wherein the QD layers are located vertically adjacent to the first III-V semiconductor layers and wherein the active components are optically coupled to one another via the passive components.

13. The method of claim 12 , further including:
selectively intermixing the QD layer with adjacent III-V layers in areas corresponding with one or more active components to modify the bandgap associated with the intermixed QD layer.

14. The method of claim 12 , wherein epitaxially depositing the III-V semiconductor layers includes depositing p-doped barrier layers between the one or more layers of quantum dots.

15. The method of claim 12 , further including:
patterning a planar surface associated with the semiconductor substrate in a region associated with either the first active optical component or the second active optical component prior to epitaxially depositing the III-V semiconductor layers.

16. A method of fabricating a monolithically integrated photonic integrated circuit (PIC), the method comprising:
epitaxially depositing first III-V semiconductor layers on a semiconductor substrate;
processing the first III-V semiconductor layers to form a passive optical component;
epitaxially depositing second III-V semiconductor layers on top of the first III-V semiconductor layers; and
processing the second III-V semiconductor layers to form at least first and second active optical components, wherein processing of the second III-V semiconductor layers includes fabricating one or more layers of quantum dots (QD) separated by one or more barrier layers.

17. The method of claim 16 , wherein epitaxially depositing the second III-V semiconductor layers includes depositing p-doped barrier layers between the one or more layers of quantum dots.

18. The method of claim 16 , further including patterning a planar surface associated with the first III-V semiconductor layers in a region associated with at least one of the first active optical component or the second active optical component prior to deposition of the second III-V semiconductor layer onto the first III-V semiconductor layer.

19. The method of claim 16 , wherein processing the second III-V semiconductor layers associated with at least one of the first active optical component or second active optical component includes inducing point defects to encourage interdiffusion between the one or more layers of quantum dots and one or more barrier layers.

Assignees

• Univ California

Inventors

• Bowers John E
• Gossard Arthur
• Jung Daehwan
• Norman Justin
• Shang Chen
• Wan Yating

Classifications

• H01S5/026

  Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers (stabilisation of output H01S5/06) · CPC title

• H01S5/3412

  quantum box or quantum dash · CPC title

• G02B6/13

  Integrated optical circuits characterised by the manufacturing method · CPC title

• B82Y20/00

  Nanooptics, e.g. quantum optics or photonic crystals · CPC title

• H01S5/021 Primary

  Silicon based substrates · CPC title