Clock signal generation circuit, method for generating clock signal and electronic device

Patent metadata

Field	Value
Publication number	US-11689193-B2
Application number	US-202117765933-A
Country	US
Kind code	B2
Filing date	Mar 9, 2021
Priority date	Apr 3, 2020
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

A clock signal generation circuit, a method for generating a clock signal, and an electronic device are provided, relating to the field of communications technology. In the clock signal generation circuit, an initial clock providing circuit can generate an initial clock signal having an initial frequency; a control word providing circuit can determine a target frequency offset of the initial frequency based on a detected target parameter and generate a frequency control word based on the target frequency offset; a target clock generating circuit can generate a target clock signal having a target output frequency based on the frequency control word and the initial clock signal, wherein the target output frequency is negatively correlated with a value of the frequency control word and positively correlated with the initial frequency.

First claim

What is claimed is:

1. A clock signal generation circuit, comprising: an initial clock providing circuit, a control word providing circuit and a target clock generating circuit, wherein
the initial clock providing circuit is connected to the target clock generating circuit, and the initial clock providing circuit is configured to: generate an initial clock signal having an initial frequency, and output the initial clock signal to the target clock generating circuit;
the control word providing circuit is connected to the target clock generating circuit, and the control word providing circuit is configured to: detect a target parameter affecting a frequency offset of the initial frequency, determine a target frequency offset of the initial frequency based on the target parameter, generate a frequency control word based on the target frequency offset, and output the frequency control word to the target clock generating circuit; and
the target clock generating circuit is configured to generate a target clock signal having a target output frequency based on the frequency control word and the initial clock signal, wherein the target output frequency is negatively correlated with a value of the frequency control word and positively correlated with the initial frequency.

2. The clock signal generation circuit according to claim 1 , wherein the target output frequency fs satisfies: fs=fc/F, wherein fc is the initial frequency and F is the value of the frequency control word.

3. The clock signal generation circuit according to claim 1 , wherein the target parameter comprises a temperature, and the control word providing circuit comprises a temperature detecting sub-circuit, a frequency offset determining sub-circuit and a control word generating sub-circuit;
the temperature detecting sub-circuit is connected to the frequency offset determining sub-circuit, and the temperature detecting sub-circuit is configured to: detect a target temperature, and output the target temperature to the frequency offset determining sub-circuit;
the frequency offset determining sub-circuit is further connected to the control word generating sub-circuit, and the frequency offset determining sub-circuit is configured to: determine the target frequency offset of the initial frequency based on the target temperature, and output the target frequency offset to the control word generating sub-circuit; and
the control word generating sub-circuit is further connected to the target clock generating circuit, and the control word generating sub-circuit is configured to: generate the frequency control word based on the target frequency offset, a historical frequency control word and a reference output frequency, output the frequency control word to the target clock generating circuit, and update the historical frequency control word with the frequency control word, wherein
a value of the frequency control word F satisfies: F=F0+Δf/fs', F0 is a value of the historical frequency control word, Δf is the target frequency offset, and fs' is the reference output frequency.

4. The clock signal generation circuit according to claim 3 , wherein the frequency offset determining sub-circuit comprises a controller and a memory, and the memory stores a plurality of candidate frequency offsets in a one-to-one correspondence with a plurality of different temperatures; and
the controller is respectively connected to the memory and the control word generating sub-circuit, and the controller is configured to: search for a target candidate frequency offset corresponding to the target temperature from the plurality of candidate frequency offsets stored in the memory, determine the target candidate frequency offset as the target frequency offset, and output the target frequency offset to the control word generating sub-circuit.

5. The clock signal generation circuit according to claim 4 , wherein the memory has a plurality of storage areas, each of the storage areas stores one candidate frequency offset, and candidate frequency offsets stored in different storage areas are different; and
the controller is configured to: determine an address of a target storage area from the plurality of storage areas based on the target temperature, and acquire the target frequency offset from the target storage area based on the address of the target storage area, wherein the address A1 of the target storage area satisfies: A1=T/r+A0, A0 is a reference address, T is the target temperature, and r is a detection resolution of the temperature detecting sub-circuit.

6. The clock signal generation circuit according to claim 3 , wherein the frequency offset determining sub-circuit is configured to determine a target frequency offset in each detection period based on the target temperature output by the temperature detecting sub-circuit; and
the control word generating sub-circuit is further configured to: determine whether the target frequency offset is equal to a historical frequency offset, and generate the frequency control word based on the target frequency offset, the historical frequency control word and the reference output frequency if the target frequency offset is not equal to the historical frequency offset, wherein
the historical frequency offset is a target frequency offset determined by the frequency offset determining sub-circuit in a previous detection period.

7. The clock signal generation circuit according to claim 6 , wherein the control word generating sub-circuit comprises: a register, a comparator and a control word generating unit;
the register is respectively connected to the frequency offset determining sub-circuit, the comparator and the control word generating unit, and the register is configured to: output the historical frequency offset to the comparator, output the target frequency offset generated by the frequency offset determining sub-circuit to the control word generating unit, and update the historical frequency offset with the target frequency offset;
the comparator is further respectively connected to the frequency offset determining sub-circuit and the control word generating unit, and the comparator is configured to: determine whether the target frequency offset is equal to the historical frequency offset, and output an enable signal to the control word generating unit if the target frequency offset is not equal to the historical frequency offset; and
the control word generating unit is further connected to the target clock generating circuit, and the control word generating unit is configured to: generate the frequency control word in response to the enable signal based on the target frequency offset, the historical frequency control word and the reference output frequency, output the frequency control word to the target clock generating circuit, and update the historical frequency control word with the frequency control word.

8. The clock signal generation circuit according to claim 7 , wherein the target output frequency fs satisfies: fs=fc/F, wherein fc is the initial frequency and F is the value of the frequency control word;
the frequency offset determining sub-circuit comprises a controller and a memory, the memory has a plurality of storage areas, each of the storage areas stores one candidate frequency offset, and candidate frequency offsets stored in different storage areas are different;
the controller is respectively connected to the memory and the control word generating sub-circuit, and the controller is configured to: determine an address of a target storage area from the plurality of storage areas based on the target temperature, and acquire the target frequency offset from the target storage area based on the address of the target storage area, wherein
the address A1 of the target s

Assignees

• Beijing Boe Technology Dev Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wei Xiangye
• Xiu Liming

Classifications

• H03K3/011 Primary

  Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature {(to maintain energy constant H03K3/015)} · CPC title

• H03K5/26

  the characteristic being duration, interval, position, frequency, or sequence · CPC title

• H03K5/249 Primary

  using clock signals · CPC title

• H03L7/24 Primary

  using a reference signal directly applied to the generator · CPC title

• H03K3/02

  Generators characterised by the type of circuit or by the means used for producing pulses (H03K3/64 - H03K3/84 take precedence) · CPC title