Time synchronization device, electronic apparatus, time synchronization system and time synchronization method

Patent metadata

Field	Value
Publication number	US-11429137-B2
Application number	US-201916620547-A
Country	US
Kind code	B2
Filing date	Apr 16, 2019
Priority date	Jun 11, 2018
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

A time synchronization device adapted for an electronic apparatus, an electronic apparatus, a time synchronization system and a time synchronization method. The time synchronization device includes: a signal generating circuit and a time adjusting circuit. The signal generating circuit includes: a control circuit, configured to generate a frequency control word; and a signal adjusting circuit, configured to receive the frequency control word and an input signal having an initial frequency, and to generate and output an output signal having a target frequency based on the frequency control word and the input signal. The time adjusting circuit is configured to perform a synchronization adjusting operation on a clock signal of the electronic apparatus based on the output signal having the target frequency.

First claim

What is claimed is:

1. A time synchronization device adapted for an electronic apparatus, the time synchronization device comprising: a signal generating circuit and a time adjusting circuit, wherein the signal generating circuit comprises:
a control circuit, configured to generate a frequency control word; and
a signal adjusting circuit, configured to receive the frequency control word and an input signal having an initial frequency, and to generate and output an output signal having a target frequency based on the frequency control word and the input signal, and
the time adjusting circuit is configured to perform a synchronization adjusting operation on a clock signal of the electronic apparatus based on the output signal having the target frequency.

2. The time synchronization device according to claim 1 , wherein the control circuit is configured to generate the frequency control word based on an influence parameter of crystal oscillator drift.

3. The time synchronization device according to claim 2 , wherein the signal generating circuit further comprises a parameter acquiring circuit, and the parameter acquiring circuit is configured to acquire the influence parameter.

4. The time synchronization device according to claim 3 , wherein
the influence parameter of the crystal oscillator drift comprises a temperature parameter;
the parameter acquiring circuit comprises a temperature detecting sub-circuit; and
the temperature detecting sub-circuit is configured to detect the temperature parameter.

5. The time synchronization device according to claim 4 , wherein
the temperature parameter comprises the ambient temperature;
the temperature detecting sub-circuit comprises a temperature detector and a first counter;
the temperature detector is configured to detect the ambient temperature; and
the first counter is configured to record a frequency change amount based on the ambient temperature and a reference temperature.

6. The time synchronization device according to claim 5 , wherein the control circuit is configured to generate the frequency control word based on the ambient temperature according to a below equation:

F
N

=

F
TO

·

f
Δ

+

Δ
⁢

⁢

f
·

F
TO
2

f
Δ

where F N denotes the frequency control word; F TO denotes a reference frequency control word corresponding to the reference temperature; and f Δ denotes a frequency of a reference time unit; and
Δ f=r·ΔT n +p·ΔT n-1 + . . . +d·ΔT+g

where Δf denotes the frequency change amount; r, p, d and g are constants; ΔT denotes a difference between the ambient temperature and the reference temperature, ΔT=T 1 −T 2 ; T 1 denotes the ambient temperature; T 2 denotes the reference temperature; and n is a positive integer.

7. The time synchronization device according to claim 3 , wherein
the influence parameter of the crystal oscillator drift comprises an aging parameter;
the parameter acquiring circuit comprises an aging read sub-circuit; and
the aging read sub-circuit is configured to read the aging parameter of a crystal oscillator source.

8. The time synchronization device according to claim 7 , wherein
the aging parameter comprises an aging rate of the crystal oscillator and reference time corresponding to the aging rate of the crystal oscillator;
the aging read sub-circuit comprises an aging read element and a second counter;
the aging read element is configured to read the aging rate of the crystal oscillator source, and to read the reference time; and
the second counter is configured to record an amount of the reference time.

9. The time synchronization device according to claim 8 , wherein the control circuit is configured to generate the frequency control word based on the aging rate according to a below equation:
F N =F AO ·(1+γ)

where F N denotes the frequency control word; F AO denotes the reference frequency control word; γ denotes a product of the aging parameter, wherein γ=v·t, v denotes the aging rate, t denotes the amount of the reference time, and t is a natural number.

10. The time synchronization device according to claim 2 , wherein the signal adjusting circuit comprises a reference time unit generating sub-circuit and a frequency adjusting sub-circuit;
the reference time unit generating sub-circuit is configured to receive the input signal having the initial frequency, and to generate and output the reference time unit based on the initial frequency; and
the frequency adjusting sub-circuit is configured to generate and output the output signal having the target frequency based on the frequency control word and the reference time unit.

11. The time synchronization device according to claim 1 , wherein the signal adjusting circuit comprises a reference time unit generating sub-circuit and a frequency adjusting sub-circuit,
the reference time unit generating sub-circuit is configured to receive the input signal having the initial frequency, and to generate and output the reference time unit based on the initial frequency; and
the frequency adjusting sub-circuit is configured to generate and output the output signal having the target frequency based on the frequency control word and the reference time unit.

12. The time synchronization device according to claim 11 , wherein the reference time unit generating sub-circuit comprises:
a voltage controlled oscillator, configured to oscillate at a predetermined oscillation frequency;
a first phase locked loop circuit, configured to lock an output frequency of the voltage controlled oscillator to a reference output frequency; and
K output terminals, configured to output K output signals having phases evenly spaced, K being a positive integer greater than 1,
wherein the reference output frequency is denoted as f d , the reference time unit is a time span between any two adjacent output signals output by the K output terminals, the reference time unit is denoted as Δ, and Δ=1/(K·f d ).

13. The time synchronization device according to claim 12 , wherein the frequency adjusting sub-circuit is configured to determine the target frequency based on the frequency control word and the reference time unit based on a below equation:
f TAF-DPS =1/( F ·Δ)=( K·f d )/ F

where f TAF-DPS denotes the target frequency, and F denotes the frequency control word.

14. The time synchronization device according to claim 12 , wherein the frequency adjusting sub-circuit comprises a time-average-frequency direct period synthesizer.

15. The time synchronization device according to claim 11 , wherein the reference time unit generating sub-circuit comprises: a voltage controlled delayer, a s

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wei Xiangye

Classifications

• H04L7/027

  extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit · CPC title

• H04J3/0667

  Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays (arrangements for monitoring round trip delays in packet switching networks H04L43/0864) · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H04J3/0638 Primary

  Clock or time synchronisation among nodes; Internode synchronisation (synchronization for ring networks H04L12/422; data switching networks with synchronous transmission H04L12/43) · CPC title