IC including capacitor having segmented bottom plate

Patent metadata

Field	Value
Publication number	US-11688760-B2
Application number	US-202117409080-A
Country	US
Kind code	B2
Filing date	Aug 23, 2021
Priority date	Aug 23, 2021
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

First claim

The invention claimed is:

1. An integrated circuit (IC), comprising:
a substrate including a semiconductor surface including circuitry having nodes coupled to bond pads, wherein the circuitry is configured to provide a receiver circuit or a transmitter circuit;
a metal stack over the semiconductor surface including a top metal layer and a plurality of lower metal layers, and
a segmented isolation capacitor, comprising:
the top metal layer as a top plate electrically connected to a first node of the nodes;
a top dielectric layer on the top plate with a top plate dielectric aperture;
one of the plurality of lower metal layers as a bottom plate, wherein the bottom plate comprises a plurality of spaced apart segments; and
a capacitor dielectric layer between the top plate and the bottom plate;

wherein the plurality of spaced apart segments include a first segment electrically connected to a second node of the nodes and at least a second segment electrically connected to a third node of the nodes, with separation regions located between adjacent ones of the plurality of spaced apart segments, and
wherein the top plate covers at least a portion of each of the separation regions.

2. The IC of claim 1 , wherein the separation regions have a width of 0.5 μm to 5 μm.

3. The IC of claim 1 , wherein the first node comprises a high supply voltage rail for the IC.

4. The IC of claim 1 , wherein the segmented isolation capacitor has a total capacitance of 10 to 1,000 fF.

5. The IC of claim 1 , wherein the semiconductor surface includes the receiver circuit that also includes a gate driver circuit, and wherein the second node or the third node of the nodes is for an electrical connection to a digital controller that connects to the gate driver circuit for adaptively controlling an output of the gate driver circuit.

6. The IC of claim 1 , wherein the second node electrically connects to a slew rate sensing block or to a voltage attenuator.

7. The IC of claim 1 , further comprising an isolation ring comprising the one of the plurality of lower metal layers that surround the plurality of spaced apart segments, wherein the isolation ring is electrically connected to a ground of the IC or a ground pin of an associated semiconductor package.

8. The IC of claim 1 , wherein a thickness of the capacitor dielectric layer is at least 4 μm, and wherein the segmented isolation capacitor sustains a DC voltage of at least 1,000V DC.

9. The IC of claim 1 , wherein the capacitor dielectric layer comprises silicon oxide.

10. A packaged multichip module (MCM), comprising:
a first integrated circuit (IC) die on a first die pad including circuitry with a metal stack thereon including a first top metal layer and a plurality of first lower metal layers;
a second IC die on a second die pad including circuitry with a metal stack thereon including a second top metal layer and a plurality of second lower metal layers;
wherein the second IC includes a segmented isolation capacitor utilizing the second top metal layer as a top plate, and a top dielectric layer thereon with a top plate dielectric aperture, with one of the plurality of second lower metal layers as a bottom plate;
the segmented isolation capacitor, comprising:
the second top metal layer as a top plate electrically connected to a first node;
one of the plurality of second lower metal layers as a bottom plate, wherein the bottom plate comprises a plurality of spaced apart segments, and
a capacitor dielectric layer between the top plate and the bottom plate;

wherein the plurality of spaced apart segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent ones of the plurality of spaced apart segments, and
wherein the top plate covers at least a portion of each of the separation regions;
a first end of a bondwire coupled within the top plate dielectric aperture on the top plate; and
a second end of the bondwire coupled to a pin of the packaged MCM.

11. The packaged MCM of claim 10 , wherein the separation regions have a width of 0.5 μm to 5 μm.

12. The packaged MCM of claim 10 , wherein the capacitor dielectric layer comprises silicon oxide.

13. The packaged MCM of claim 10 , wherein a thickness of the capacitor dielectric layer is at least 4 μm, and wherein the segmented isolation capacitor sustains a DC voltage of at least 1,000 V DC.

14. The packaged MCM of claim 10 , wherein the first IC die comprises a transmitter and the second IC die comprises a receiver.

Assignees

• Texas Instruments Inc

Inventors

• West Jeffrey
• Das Mrinal
• Williams Byron
• Bonifield Thomas
• Franke Maxim

Classifications

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title