Forming a panel of triple stack semiconductor packages

Patent metadata

Field	Value
Publication number	US-9691748-B2
Application number	US-201614988192-A
Country	US
Kind code	B2
Filing date	Jan 5, 2016
Priority date	Nov 4, 2014
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A method for forming a panel of stacked semiconductor packages includes providing a bottom leadframe (LF) panel including LFs downset each including at least a plurality of terminals. Low side (LS) transistors are attached to the first die attach area. A first clip panel including first clips downset and interconnected are placed on the bottom LF panel. A dielectric interposer is attached on the first clips over the LS transistors. High side (HS) transistors are attached on the interposers. A second clip panel including a plurality of second clips is mated to interconnect to the HS transistors including mating together the second clip panel, first clip panel and bottom LF panel. The LFs can include a second die attach area, and a controller die attached on the second die attach area, and then pads of the controller die wirebonded to the plurality of terminals.

First claim

The invention claimed is:

1. A method for forming a panel of stacked semiconductor packages, comprising:
providing a bottom leadframe (LF) panel including an interconnected plurality of LFs downset each including at least a first die attach area, and a plurality of terminals;
attaching a plurality of low side (LS) transistors to said first die attach area;
placing a first clip panel including a plurality of first clips downset and interconnected on said bottom LF panel;
attaching a dielectric interposer (interposer) on each of said plurality of first clips over said LS transistors;
attaching a plurality of high side (HS) transistors on said interposers, and
mating a second clip panel including a plurality of second clips to interconnect to said HS transistors including mating together said second clip panel, said first clip panel and said bottom LF panel.

2. The method of claim 1 , wherein said plurality of LFs further include a second die attach area, further comprising after said mating:
attaching a controller die on each of said second die attach area, and
wire bonding bond pads of said controller die to ones of said plurality of terminals.

3. The method of claim 1 , further comprising molding with a mold material and then sawing to form a plurality of said stacked semiconductor packages, wherein a flexure of said LFs and said first clips during said molding is at least 0.025 mm.

4. The method of claim 1 , wherein said LFs and said first clips are downset to a different extent.

5. The method of claim 1 , wherein said bottom LF panel, said first clip panel and said second clip panel all have alignment holes in at least one of their rails, and wherein said mating utilizes said alignment holes for alignment.

6. The method of claim 1 , wherein said bottom LF panel comprises a Quad Flat No Lead (QFN) or a dual-flat no-lead (DFN).

7. The method of claim 1 , wherein said LS and said HS transistors both comprise field effect transistors (FETs).

8. The method of claim 1 , wherein the first clip panel comprises a plurality of interconnected first clips.

9. The method of claim 8 , wherein the second clip panel comprises a plurality of interconnected second clips.

10. The method of claim 1 , wherein the second clip panel comprises a plurality of interconnected second clips.

Assignees

• Texas Instruments Inc

Inventors

• Eugene Lee Lee Han Meng @
• Bin Abdul Aziz Anis Fauzi
• Fen Sueann Lim Wei

Classifications

• H10W72/60

  Strap connectors, e.g. thick copper clips for grounding of power devices · CPC title

• H10W72/07653

  changes in shapes · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/075

  of bond wires · CPC title