Wafer level testing of optical components

US11688652B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11688652-B2
Application numberUS-202217653524-A
CountryUS
Kind codeB2
Filing dateMar 4, 2022
Priority dateJul 20, 2018
Publication dateJun 27, 2023
Grant dateJun 27, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A system may include a wafer that includes ICs and defines cavities. Each cavity may be formed in a BEOL layer of the wafer and proximate a different IC. The system may also include an interposer that includes a transparent layer configured to permit optical signals to pass through. The interposer may also include at least one waveguide located proximate the transparent layer. The at least one waveguide may be configured to adiabatically couple at least one optical signal out of the multiple ICs. Further, the interposer may include a redirecting element optically coupled to the at least one the waveguide. The redirecting element may be located proximate the transparent layer and may be configured to receive the at least one optical signal from the at least one waveguide. The redirecting element may also be configured to vertically redirect the at least one optical signal towards the transparent layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A system comprising: a wafer comprising a plurality of integrated circuits (ICs) and the wafer defining a plurality of cavities, each cavity of the plurality of cavities being formed in a back end of line (BEOL) layer of the wafer proximate a different IC of the plurality of ICs; and an interposer configured to test the plurality of ICs and the interposer being configured to be placed in one cavity of the plurality of cavities at a time proximate a corresponding IC of the plurality of ICs, the interposer comprising: a transparent layer configured to permit optical signals to pass through; at least one waveguide located proximate the transparent layer, the at least one waveguide configured to adiabatically couple at least one optical signal out the plurality of ICs; and a redirecting element optically coupled to the at least one waveguide and located proximate the transparent layer, the redirecting element configured to receive the at least one optical signal from the at least one waveguide and to vertically redirect the at least one optical signal towards the transparent layer. 2. The system of claim 1 , the system further comprising an optical component located proximate the transparent layer and vertically above the redirecting element, the optical component configured to receive the at least one redirected optical signal. 3. The system of claim 2 , wherein the optical component is configured to provide an electrical signal to an external device, the electrical signal representative of the at least one redirected optical signal. 4. The system of claim 2 , wherein the optical component comprises at least one of a photo-detector, a photodiode, and an optical fiber. 5. The system of claim 1 , wherein: the at least one optical signal comprises a first optical signal and the at least one waveguide comprises a first waveguide and a second waveguide, the first waveguide is configured to adiabatically couple the first optical signal out of a corresponding IC of the plurality of ICs; and the system further comprises a testing fixture located proximate the transparent layer, the testing fixture configured to provide a second optical signal, the second waveguide configured to receive the second optical signal and to adiabatically couple the second optical signal into the corresponding IC of the plurality of ICs. 6. The system of claim 1 , wherein each IC of the plurality of ICs comprises one or more adiabatic couplers and the at least one waveguide is configured to adiabatically couple the at least one optical signal out of at least one adiabatic coupler of the one or more adiabatic couplers in a corresponding IC of the plurality of ICs. 7. The system of claim 6 , wherein the plurality of cavities are formed in the wafer such that a portion of a front end of line (FEOL) layer of the wafer is located above the one or more adiabatic couplers in each IC of the plurality of ICs and the portion of the FEOL layer is thin enough to enable optical coupling between the one or more adiabatic couplers in each IC of the plurality of ICs and the at least one waveguide in the interposer. 8. The system of claim 1 , wherein: the redirecting element comprises a grating coupler configured to redirect the at least one optical signal; and the interposer further comprises a mirror located below the grating coupler, wherein the mirror is configured to reduce degradation of the at least one redirected optical signal. 9. The system of claim 1 , wherein the redirecting element comprises a mirror configured to vertically redirect the at least one optical signal towards the transparent layer. 10. The system of claim 1 , the system further comprising a removable material configured to assist in optically coupling the at least one waveguide with the plurality of ICs. 11. The system of claim 1 , wherein the at least one optical signal comprises a first optical signal and the at least one waveguide comprises: a first waveguide configured to adiabatically couple the first optical signal out of a corresponding IC of the plurality of ICs; and a second waveguide optically coupled to the first waveguide and the redirecting element, the second waveguide located proximate the first waveguide with a portion of the transparent layer positioned between the first waveguide and the second waveguide, the second waveguide being configured to adiabatically couple the first optical signal out of the first waveguide and to provide the first optical signal to the redirecting element. 12. The system of claim 11 , the interposer further comprising: a thick substrate configured to permit optical signals to pass through; and an anti-reflection (AR) coating located on a top surface of the transparent layer between the thick substrate and the transparent layer. 13. The system of claim 12 , wherein the redirecting element comprises a grating coupler optically coupled to the second waveguide and located within the transparent layer, the grating coupler configured to receive the at least one optical signal from the second waveguide and to vertically redirect the at least one optical signal towards the thick substrate. 14. The system of claim 1 , wherein each IC of the plurality of ICs comprise at least one of a photonic integrated circuit and an optical integrated circuit. 15. A system comprising: a wafer having a plurality of adiabatic couplers, the adiabatic couplers being configured to communicate optical signals for integrated circuits, the wafer having a back end of line (BEOL) layer and defining a plurality of cavities formed in the BEOL layer, each of the cavities being proximate at least one of the adiabatic couplers; and a testing fixture being configured to test each of the integrated circuits and having an interposer, the interposer being configured to position in each of the cavities one at a time proximate the at least one adiabatic coupler, the interposer comprising: a transparent layer configured to permit the optical signals to pass through; at least one waveguide located proximate the transparent layer and being configured to adiabatically couple the optical signals with the at least one adiabatic coupler; and a directing element optically coupled to the at least one waveguide and located proximate the transparent layer, the directing element being configured to direct the optical signals between a horizontal direction towards the at least one waveguide and a vertical direction towards the transparent layer. 16. The system of claim 15 , wherein the testing fixture comprises an optical component located proximate the transparent layer and located vertically above the directing element, the optical component configured to measure the optical signals directed thereto. 17. The system of claim 15 , wherein the at least one waveguide comprises first and second waveguides; and wherein the at least one adiabatic coupler in a corresponding one of the cavities comprises first and second adiabatic couplers, the first waveguide being configured to adiabatically couple a first of the optical signals out of the first adiabatic coupler, the second waveguide being configured to adiabatically couple a second of the optical signals into the second adiabatic coupler. 18. The system of claim 15 , wherein the directing element comprises: a grating coupler optically coupled to the at least one waveguide and being configured to direct the optical signals, and a mirror located below the grating coupler and being configured to reduce degradation of the optical signals directed by the grating

Assignees

Inventors

Classifications

  • Structural arrangements therefor · CPC title

  • H10P74/207Primary

    Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

  • Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

  • Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

  • H01L22/14Primary

    Electricity · mapped topic

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What does patent US11688652B2 cover?
A system may include a wafer that includes ICs and defines cavities. Each cavity may be formed in a BEOL layer of the wafer and proximate a different IC. The system may also include an interposer that includes a transparent layer configured to permit optical signals to pass through. The interposer may also include at least one waveguide located proximate the transparent layer. The at least one …
Who is the assignee on this patent?
Ii Vi Delaware Inc
What technology area does this patent fall under?
Primary CPC classification H10P74/207. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 27 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).