Compact and efficient CMOS inverter

Patent metadata

Field	Value
Publication number	US-11688649-B2
Application number	US-202217687708-A
Country	US
Kind code	B2
Filing date	Mar 7, 2022
Priority date	Mar 31, 2020
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

A method for manufacturing an inverter circuit includes providing a semiconductor substrate and forming at least one dielectric trench isolation structure in the semiconductor substrate to divide the semiconductor substrate into first and second regions. A P+ doped portion and an N+ doped portion is formed in each of the first and second regions. Gate structure layers are then deposited over the semiconductor substrate. A first opening is formed in the gate structure layers over the P+ doped portion of a first region and a second opening is formed in the gate structure layers over the N+ doped portion of a second region. A gate dielectric layer is then formed on an inner side of the first and second openings. The surface of the semiconductor substrate in the first and second openings is etched. A semiconductor material is formed in the first and second openings by selective epitaxial growth.

First claim

The invention claimed is:

1. A method for manufacturing an inverter circuit, the method comprising:
providing a semiconductor substrate;
forming at least one dielectric trench isolation structure in the semiconductor substrate to divide the semiconductor substrate into first and second regions;
forming a P+ doped portion and an N+ doped portion in each of the first and second regions;
depositing gate structure layers over the semiconductor substrate;
forming a first opening in the gate structure layers over the P+ doped portion of a first region and forming a second opening in the gate structure layers over the N+ doped portion of a second region;
forming a gate dielectric layer on an inner side of the first and second openings;
etching a surface of the semiconductor substrate in the first and second openings; and
forming a semiconductor material in the first and second openings by selective epitaxial growth.

2. The method according to claim 1 , wherein the N+ portions and the P+ doped portions are arranged such that each doping type region is located adjacent to an opposite doping type region.

3. The method according to claim 1 , wherein the P+ doped portion of a first region is adjacent to the N+ doped portion of a second region along a direction perpendicular to an alignment of the P+ doped portion and N+ doped portion in the first region, and the N+ doped portion of the first region is adjacent to the P+ doped portion of the second region along a same direction.

4. The method according to claim 1 , wherein forming a P+ doped portion and an N+ doped portion in each of the first and second regions comprises: forming a first mask and ion implanting N+ doping material, and forming a second mask and ion implanting P+ doping material.

5. The method according to claim 1 , wherein the first and second openings are formed with a rectangular shape.

6. The method according to claim 1 , wherein the etching of the surface of the semiconductor substrate in the first and second openings is performed so as to form a beveled surface on the semiconductor substrate within the first and second openings.

7. The method according to claim 1 , wherein the etching of the surface of the semiconductor substrate comprises reactive ion etching.

8. The method according to claim 1 , wherein forming the gate dielectric layer further comprises:
depositing a gate dielectric material;
depositing a protective layer over the gate dielectric material;
performing an anisotropic etching to remove the gate dielectric material and the protective layer from a bottom of the first and second openings; and
performing an anisotropic etching to remove the protective layer.

9. The method according to claim 8 , wherein the gate dielectric material comprises one or more of an oxide or nitride.

10. The method according to claim 8 , wherein the gate dielectric material is deposited by sputter deposition, chemical vapor deposition, or atomic layer deposition.

11. The method according to claim 8 , wherein the anisotropic etching comprises ion beam etching.

12. The method according to claim 8 , wherein the isotropic etching comprises reactive ion etching.

13. The method according to claim 1 , further comprising: performing a masking and etching process to remove a portion of the gate structure layers to form a gate line structure.

14. The method according to claim 13 , wherein the gate line structure connects with the gate dielectric layer formed over each of the first and second regions.

15. The method according to claim 1 , wherein the gate structure layers comprise a first dielectric layer, an electrically conductive gate layer formed over the first dielectric layer, and a second dielectric layer formed over the electrically conductive gate layer.

16. The method according to claim 15 , further comprising:
forming a Vin lead, electrically connected with the electrically conductive gate layer;
forming a Vout lead electrically connected with the epitaxially grown semiconductor material over each of the first and second regions;
forming a Vss lead electrically connected with the N+ and P+ doped portions of the second region; and
forming a Vdd lead electrically connected with the P+ and N+ doped portions of the first region.

17. The method according to claim 16 , further comprising, before forming the Vin lead, Vout lead, Vss lead, and Vdd lead, forming a first contact structure for connecting the Vin lead with the electrically conductive gate layer, forming a second set of contact structures for electrically connecting the Vout lead with the epitaxially grown semiconductor material over each of the first and second regions, forming a third set of contact structures for electrically connecting the Vss lead with the N+ and P+ doped portions of the second region, and forming a fourth set of contact structures for electrically connecting the Vdd lead with the P+ and N+ doped portions of the first region.

18. The method according to claim 1 , wherein the formed semiconductor material comprises at least 80 percent monocrystalline by volume.

19. The method according to claim 1 , wherein the formed semiconductor material comprises at least 90 percent monocrystalline by volume.

20. The method according to claim 1 , wherein the at least one dielectric trench isolation structure formed in the semiconductor substrate is deeper than the P+ doped portion and an N+ doped portion formed in each of the first and second regions in the semiconductor substrate.

Assignees

• Integrated Silicon Solution Cayman Inc

Inventors

• Levi Amitay
• Beery Dafna
• Walker Andrew J

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title