Gate structure of a semiconductor device and method of forming same

Patent metadata

Field	Value
Publication number	US-11688648-B2
Application number	US-202217671145-A
Country	US
Kind code	B2
Filing date	Feb 14, 2022
Priority date	Jun 29, 2020
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

A semiconductor device having a gate structure and a method of forming same are provided. The semiconductor device includes a substrate and a gate structure over the substrate. The substrate has a first region and a second region. The gate structure extends across an interface between the first region and the second region. The gate structure includes a first gate dielectric layer over the first region, a second gate dielectric layer over the second region, a first work function layer over the first gate dielectric layer, a barrier layer along a sidewall of the first work function layer and above the interface between the first region and the second region, and a second work function layer over the first work function layer, the barrier layer and the second gate dielectric layer. The second work function layer is in physical contact with a top surface of the first work function layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate, the substrate having a first region and a second region; and
a gate structure over the substrate, the gate structure extending across an interface between the first region and the second region, the gate structure comprising:
a first gate dielectric layer over the first region;
a second gate dielectric layer over the second region;
a first work function layer over the first gate dielectric layer;
a second work function layer over the first work function layer and the second gate dielectric layer, wherein the second work function layer is in physical contact with a top surface of the first work function layer and a top surface of the second gate dielectric layer;
a barrier layer along a sidewall of the second work function layer, wherein the barrier layer is above the interface between the first region and the second region; and
a third work function layer over the second work function layer and the barrier layer, wherein the third work function layer is in physical contact with a top surface of the second work function layer and a top surface and a sidewall of the barrier layer.

2. The semiconductor device of claim 1 , wherein the top surface of the barrier layer is substantially level with the top surface of the second work function layer.

3. The semiconductor device of claim 1 , wherein the top surface of the barrier layer is lower than the top surface of the second work function layer.

4. The semiconductor device of claim 1 , wherein the barrier layer has a rounded corner.

5. The semiconductor device of claim 1 , wherein the gate structure further comprises:
a first shield layer over the third work function layer, wherein the first shield layer is over the first gate dielectric layer; and
a second shield layer over the third work function layer, wherein the second shield layer is over the second gate dielectric layer.

6. The semiconductor device of claim 5 , wherein the gate structure further comprises:
a first glue layer over the first shield layer; and
a second glue layer over the second shield layer.

7. The semiconductor device of claim 6 , wherein the gate structure further comprises:
a first conductive layer over the first glue layer; and
a second conductive layer over the second glue layer.

8. A semiconductor device comprising:
a substrate, the substrate having a first region and a second region; and
a gate structure over the substrate, wherein a first portion of the gate structure is above the first region and a second portion of the gate structure is above the second region, and wherein the gate structure comprises:
a first gate dielectric layer over the first region;
a second gate dielectric layer over the second region;
a first p-type work function layer over the first gate dielectric layer, the first p-type work function layer having a sidewall above an interface between the first region and the second region;
a second p-type work function layer over the first p-type work function layer and the second gate dielectric layer, wherein the second p-type work function layer has a sidewall above the interface between the first region and the second region;
a barrier layer in physical contact with the sidewall of the second p-type work function layer, wherein the barrier layer extends along the sidewall of the second p-type work function layer not higher than to a top surface of the second p-type work function layer;
an n-type work function layer over the second p-type work function layer, wherein the n-type work function layer is in physical contact with a top surface and a sidewall of the barrier layer;
a first conductive layer over a first portion of the n-type work function layer above the first region; and
a second conductive layer over a second portion of the n-type work function layer above the second region.

9. The semiconductor device of claim 8 , wherein the top surface of the barrier layer is substantially level with the top surface of the second p-type work function layer.

10. The semiconductor device of claim 8 , wherein the top surface of the barrier layer is lower than the top surface of the second p-type work function layer.

11. The semiconductor device of claim 8 , wherein the second p-type work function layer is in physical contact with a bottom surface of the barrier layer.

12. The semiconductor device of claim 8 , wherein the second p-type work function layer is in physical contact with a top surface of the second gate dielectric layer.

13. The semiconductor device of claim 8 , wherein the first p-type work function layer and the second p-type work function layer comprise different materials.

14. The semiconductor device of claim 8 , wherein the first p-type work function layer and the second p-type work function layer comprise a same material.

15. A method comprising:
forming a sacrificial gate over a substrate, the substrate having a first region and a second region, the sacrificial gate extending across an interface between the first region and the second region;
removing the sacrificial gate to form an opening;
forming a first gate dielectric layer over the first region in the opening;
forming a second gate dielectric layer over the second region in the opening;
forming a first work function layer over the first gate dielectric layer in the opening;
forming a second work function layer over the first work function layer and the second gate dielectric layer in the opening;
depositing a dielectric layer over the second work function layer in the opening, wherein the dielectric layer comprises a first material;
patterning the dielectric layer to form a barrier layer on a sidewall of the second work function layer; and
forming a third work function layer over the second work function layer and the barrier layer.

16. The method of claim 15 , wherein patterning the dielectric layer comprises:
performing a treatment process on the dielectric layer to form a treated portion of the dielectric layer, wherein the treated portion of the dielectric layer comprises a second material different from the first material; and
selectively etching the treated portion of the dielectric layer, wherein an un-treated portion of the dielectric layer remains on the sidewall of the second work function layer and forms the barrier layer.

17. The method of claim 16 , wherein the treatment process comprises an oxidation process, a fluorination process, a nitridation process, or a chlorination process.

18. The method of claim 16 , wherein the treatment process comprises an implantation process.

19. The method of claim 15 , wherein patterning the dielectric layer comprises performing an anisotropic etch process on the dielectric layer.

20. The method of claim 15 , wherein the first work function layer and the second work function layer are p-type work function layers, and wherein the third work function layer is an n-type work function layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• More Shahaji B
• Savant Chandrashekhar Prakash
• Tsai Chun Hsiung

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P30/40

  into insulating materials · CPC title

• H10D64/01326

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10P32/30

  Diffusion for doping of conductive or resistive layers · CPC title