Structure and method to suppress work function effect by patterning boundary proximity in replacement metal gate

Patent metadata

Field	Value
Publication number	US-2017200719-A1
Application number	US-201614994650-A
Country	US
Kind code	A1
Filing date	Jan 13, 2016
Priority date	Jan 13, 2016
Publication date	Jul 13, 2017
Grant date	—

Abstract

A semiconductor device includes a first transistor formed on a substrate, the first transistor including a channel region positioned on the substrate; a second transistor formed on the substrate, the second transistor including a channel region positioned on the substrate; a high-k dielectric layer disposed on the channel region of the first transistor and the channel region of the second transistor; a first transistor metal gate positioned in contact with the high-k dielectric on the first transistor; a second transistor metal gate positioned in contact with the high-k dielectric on the second transistor; an oxygen absorbing barrier disposed in contact with the high-k dielectric between the first transistor and the second transistor; and a conductive electrode material disposed on the first transistor, the second transistor, and the oxygen absorbing barrier.

First claim

1 .- 13 . (canceled)

14 . A method of making a semiconductor device, the method comprising:
forming a first transistor channel region of a first transistor and a second transistor channel region of a second transistor on a substrate; depositing a high-k dielectric layer on the first transistor channel region and the second transistor channel region, the high-k dielectric layer extending continuously over the first transistor channel region and the second transistor channel region; forming a first transistor metal gate stack on the high-k dielectric on the first transistor; forming a second transistor metal gate stack on the high-k dielectric on the second transistor; depositing an oxygen absorbing barrier layer directly on the high-k dielectric layer extending continuously between the first transistor metal gate stack and the second transistor metal gate stack, the oxygen absorbing barrier layer positioned in direct contact with the high-k dielectric between the first transistor metal gate stack and the second transistor metal gate stack; and depositing a conductive electrode material on the first transistor and the second transistor.

15 . The method of claim 14 , wherein the first transistor is an nFET, and the second transistor is a pFET.

16 . The method of claim 14 , further comprising depositing a sacrificial material on the first transistor metal gate and the second transistor metal gate after forming the second transistor metal gate; forming an opening in the sacrificial material between the first transistor and the second transistor; and removing the first transistor metal gate and the second transistor metal gate beneath the opening to expose the high-k dielectric between the first transistor and the second transistor.

17 . The method of claim 16 , further comprising removing the sacrificial material and then depositing the oxygen absorbing barrier between the first transistor and the second transistor, wherein the oxygen absorbing barrier is also disposed on the second transistor gate stack on the first transistor and the second transistor.

18 . The method of claim 14 , wherein the conductive electrode material is deposited before depositing the oxygen absorbing barrier.

19 . The method of claim 18 , further comprising disposing a mask on the conductive electrode material; patterning the mask to form an opening between the first transistor and the second transistor; removing the conductive electrode material, the first transistor gate stack, and the second transistor gate stack beneath the opening to expose the high-k dielectric and form a trench; and removing the mask.

20 . The method of claim 19 , further comprising filling the trench with an oxygen absorbing barrier material.

21 . The method of claim 14 , wherein forming the second transistor metal gate stack further comprises depositing a portion of the second transistor metal gate stack on the first transistor metal gate stack.

22 . The method of claim 21 , wherein the oxygen absorbing barrier layer extends from the high-k dielectric layer to a top surface of the portion of the second transistor metal gate stack on the first transistor metal gate stack.

23 . The method of claim 22 , wherein the oxygen absorbing barrier layer is TiN, TiC, TiN, TiC, TaC, Ti, Al, TiAl, W, Ni, Nb, NbAl or any combination thereof.

Assignees

• IBM

Inventors

• Bao Ruqiang
• Kwon Unoh
• Zhao Kai

Classifications

• H10D84/83135

  the IGFETs characterised by having different gate conductor materials or different gate conductor implants · CPC title

• H10D64/669

  the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title

• H01L29/4966

  Electricity · mapped topic