Current flattening circuit for protection against power side channel attacks

Patent metadata

Field	Value
Publication number	US-11687679-B2
Application number	US-202218046275-A
Country	US
Kind code	B2
Filing date	Oct 13, 2022
Priority date	Apr 23, 2020
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.

First claim

What is claimed is:

1. A current flattening circuit comprising:
at least one PMOS transistor interposed between a power supply and a load;
a shunt transistor and a differential amplifier each coupled to a node between the at least one PMOS transistor and the load; and
a gate voltage of the shunt transistor configured to be controlled by the differential amplifier.

2. The current flattening circuit of claim 1 , wherein the shunt transistor is an NMOS transistor.

3. The current flattening circuit of claim 2 , wherein the differential amplifier is coupled to input a reference voltage and a load voltage.

4. A current flattening circuit comprising:
a shunt transistor coupled to receive current directly from a power supply and configured with a fixed gate bias voltage;
a load current sensor coupled to directly receive the current from the power supply and to supply current directly to a load; and
a differential amplifier coupled across the load current sensor to control a gate of the shunt transistor.

5. The current flattening circuit of claim 4 , wherein the load current sensor is a resistor.

6. The current flattening circuit of claim 4 , wherein the load current sensor is at least one PMOS transistor.

7. The current flattening circuit of claim 4 , wherein the load current sensor is a plurality of PMOS transistors.

8. The current flattening circuit of claim 4 , wherein the shunt transistor is an NMOS transistor.

9. A current flattening circuit comprising:
a load current sensor interposed between a power supply and a load;
a differential high pass filter coupled across the load current sensor, the differential high pass filter having a gain;
a differential amplifier coupled to outputs of the differential high pass filter; and
the differential amplifier coupled to drive a gate of a shunt transistor of the load.

10. The current flattening circuit of claim 9 wherein the load current sensor is a resistor.

11. The current flattening circuit of claim 9 wherein the load current sensor is a transistor.

12. The current flattening circuit of claim 11 wherein the transistor is a PMOS transistor configured with a fixed gate bias voltage.

13. The current flattening circuit of claim 9 further comprising a capacitor to the gate of the shunt transistor.

Assignees

• Nvidia Corp

Inventors

• Nedovic Nikola
• Kudva Sudhir Shrikantha

Classifications

• H02M3/155

  using semiconductor devices only · CPC title

• G06F21/755 Primary

  with measures against power attack · CPC title

• H02M1/44

  Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title