System and method to manage power throttling

Patent metadata

Field	Value
Publication number	US-11687136-B2
Application number	US-202217726924-A
Country	US
Kind code	B2
Filing date	Apr 22, 2022
Priority date	Apr 30, 2020
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.

First claim

What is claimed is:

1. A power throttling engine comprising:
a decoder configured to generate a control signal based on a value of a power throttling signal, wherein the value of the power throttling signal is an amount of power throttling of a device; and
a clock gating logic configured to receive the control signal and further configured to receive a clocking signal, and wherein the clock gating logic is configured to remove clock edges of the clocking signal by generating a throttled clocking signal based on the control signal.

2. The power throttling engine of claim 1 , wherein the throttle clocking signal is supplied as a clocking signal to the device.

3. The power throttling engine of claim 1 further comprising a phase locked loop (PLL) configured to generate the clocking signal.

4. The power throttling engine of claim 1 further comprising a shift register configured to rotate the control signal for each pulse of the clocking signal.

5. The power throttling engine of claim 4 , wherein the control signal is maintained and rotated by the shift register until a new value associated with the power throttling signal is received.

6. The power throttling engine of claim 1 , wherein the control signal comprises a plurality of binary numbers, wherein an asserted bit associated with a binary number of the control signal indicates no pulse squashing for its respective clock edge and wherein a de-asserted bit associated with a binary number of the vector indicated pulse squashing for its respective clock edge.

7. The power throttling engine of claim 1 , wherein the device is a machine learning (ML) application specific integrated circuit (ASIC).

8. The power throttling engine of claim 1 , wherein a waveform shape of the control signal is used to remove the clock edges corresponding to the waveform shape.

9. The power throttling engine of claim 1 , wherein a value associated with the control signal is used to remove the clock edges.

10. A power throttling engine comprising:
a component configured to receive a power throttling signal and a thermal sensed signal and to select one of the power throttling signal or the thermal sensed signal;
a decoder configured to generate a control signal based on a value of the selected signal, wherein the value of the selected signal is an amount of power throttling of a device; and
a clock gating logic configured to receive the control signal and further configured to receive a clocking signal, and wherein the clock gating logic is configured to remove clock edges of the clocking signal by generating a throttled clocking signal based on the control signal.

11. The power throttling engine of claim 10 , wherein the throttle clocking signal is supplied as a clocking signal to the device.

12. The power throttling engine of claim 10 further comprising a phase locked loop (PLL) configured to generate the clocking signal.

13. The power throttling engine of claim 10 further comprising a shift register configured to rotate the control signal for each pulse of the clocking signal.

14. The power throttling engine of claim 13 , wherein the control signal is maintained and rotated by the shift register until a new value associated with the selected signal is received.

15. The power throttling engine of claim 10 , wherein the control signal comprises a plurality of binary numbers, wherein an asserted bit associated with a binary number of the control signal indicates no pulse squashing for its respective clock edge and wherein a de-asserted bit associated with a binary number of the vector indicated pulse squashing for its respective clock edge.

16. The power throttling engine of claim 10 , wherein the device is a machine learning (ML) application specific integrated circuit (ASIC).

17. The power throttling engine of claim 10 , wherein the component is configured to select the power throttling signal if a value of the power throttling signal is greater than the thermal sensed signal, and wherein the component is further configured to select the thermal sensed signal if a value of the thermal sensed signal is greater than the power throttling signal.

18. The power throttling engine of claim 10 further comprising a plurality of thermal diodes configured to generate the thermal sensed signal.

19. The power throttling engine of claim 18 , wherein the plurality of thermal diodes is positioned in different quadrants of the device.

20. The power throttling engine of claim 18 , wherein the generated thermal sensed signal has a first value if a temperature as measured by the thermal diode exceeds a first threshold and wherein the thermal diode is configured to generate another thermal sensed signal after a certain period of time from the generation of the thermal sensed signal, wherein the another thermal sensed signal has a second value if a temperature as measured by the thermal diode exceeds a second threshold, and wherein the second value causes larger amount of power throttling in comparison to the first value if the second value indicates that power throttling based on the first value has cooled the device slower than anticipated.

21. The power throttling engine of claim 18 further comprising an analog to digital converter to form a digital thermal sensed signal.

22. The power throttling engine of claim 18 , wherein a thermal diode of the plurality of thermal diodes measures a temperature associated with a DDR memory, and wherein a thermal diode of the plurality of thermal diodes measures a temperature associated with the device.

23. The power throttling engine of claim 10 further comprising a thermal diode configured to generate the thermal sensed signal with a first value if a temperature as measured by the thermal diode exceeds a first threshold and wherein the thermal diode is configured to generate the thermal sensed signal with a second value if a temperature as measured by the thermal diode exceeds a second threshold.

24. The power throttling engine of claim 10 , wherein a waveform shape of the control signal is used to remove the clock edges corresponding to the waveform shape.

25. The power throttling engine of claim 10 , wherein a value associated with the control signal is used to remove the clock edges.

26. A method comprising:
receiving a power throttling signal;
receiving a thermal sensed signal;
selecting one of the power throttling signal or the thermal sensed signal;
generating a control signal based on a value of the selected signal, wherein the value of the selected signal is an amount of power throttling of a device; and
removing clock edges of a clocking signal based on the control signal to generate a throttled clocking signal.

27. A system comprising:
a means for receiving a power throttling signal;
a means for receiving a thermal sensed signal;
a means for selecting one of the power throttling signal or the thermal sensed signal;
a means for generating a control signal based on a value of the selected signal, wherein the value of the selected signal is an amount of power throttling of a device; and
a means for removing clock edges of a clocking signal based on the control signal to generate a throttled clocking signal.

Assignees

• Marvell Asia Pte Ltd

Inventors

• Sodani Avinash
• Sripada Srinivas
• Sundararaman Ramacharan
• Chen Chia-Hsin
• Jayakumar Nikhil

Classifications

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• H03L7/08

  Details of the phase-locked loop · CPC title

• G06N20/00

  Machine learning · CPC title

• G11C19/00

  Digital stores in which the information is moved stepwise, e.g. shift registers · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title