Semiconductor device package and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11682656-B2
Application number	US-202117499646-A
Country	US
Kind code	B2
Filing date	Oct 12, 2021
Priority date	Jul 26, 2019
Publication date	Jun 20, 2023
Grant date	Jun 20, 2023

Abstract

A semiconductor device package includes a substrate, a stacked structure and an encapsulation layer. The substrate includes a circuit layer, a first surface and a second surface opposite to the first surface. The substrate defines at least one cavity through the substrate. The stacked structure includes a first semiconductor die disposed on the first surface and electrically connected on the circuit layer, and at least one second semiconductor die stacked on the first semiconductor die and electrically connected to the first semiconductor die. The second semiconductor die is at least partially inserted into the cavity. The encapsulation layer is disposed in the cavity and at least entirely encapsulating the second semiconductor die.

First claim

What is claimed is:

1. A semiconductor device package, comprising:
a substrate comprising a circuit layer, the substrate including a first surface and a second surface opposite to the first surface, at least one recess recessed from the second surface and partially exposing the circuit layer, and a bottom surface of the circuit layer in the recess is recessed from the second surface of the substrate;
a first electronic component disposed above the first surface;
a second electronic component stacked adjacent to the first electronic component;
an encapsulation layer at least encapsulating the second electronic component and partially covering the second surface of the substrate; and
an electrical conductor extending from the second surface of the substrate into the recess of the substrate, and contacting the bottom surface of the circuit layer,
wherein a space is defined between the encapsulation layer and the electrical conductor.

2. The semiconductor device package of claim 1 , wherein in a cross section, a width of the space between the encapsulation layer and the electrical conductor reduces in a direction toward the substrate.

3. The semiconductor device package of claim 1 , wherein in a cross section, an interface between the space and a sidewall of the electrical conductor forms a curvature.

4. The semiconductor device package of claim 1 , wherein the space is around the electrical conductor.

5. The semiconductor device package of claim 1 , wherein a profile of the encapsulation layer at an elevation below the second surface of the substrate tapers away from the substrate.

6. The semiconductor device package of claim 1 , wherein the encapsulation layer includes a lateral surface having a section that extends toward the substrate.

7. The semiconductor device package of claim 1 , wherein the electrical conductor is in contact with an inner sidewall of the recess.

8. The semiconductor device package of claim 1 , wherein the encapsulation layer encapsulates a bottom surface of the second electronic component.

9. A semiconductor device package, comprising:
a substrate comprising a circuit layer, the substrate including a first surface and a second surface opposite to the first surface, at least one recess recessed from the second surface and partially exposing the circuit layer, and a bottom surface of the circuit layer in the recess is recessed from the second surface of the substrate;
a first electronic component disposed above the first surface;
a second electronic component stacked adjacent to the first electronic component;
an encapsulation layer at least encapsulating the second electronic component and partially covering the second surface of the substrate; and
an electrical conductor extending from the second surface of the substrate into the recess of the substrate, and contacting the bottom surface of the circuit layer, wherein a profile of the encapsulation layer at an elevation below the second surface of the substrate tapers toward the electrical conductor.

10. A semiconductor device package, comprising:
a substrate comprising a circuit layer, the substrate including a first surface and a second surface opposite to the first surface, at least one recess recessed from the second surface and partially exposing the circuit layer, and a bottom surface of the circuit layer in the recess is recessed from the second surface of the substrate;
a first electronic component disposed above the first surface;
a second electronic component stacked adjacent to the first electronic component;
an encapsulation layer at least encapsulating the second electronic component and partially covering the second surface of the substrate; and
an electrical conductor extending from the second surface of the substrate into the recess of the substrate, and contacting the bottom surface of the circuit layer, wherein a width of the substrate is less than a width of the first electronic component.

11. A semiconductor device package, comprising:
a substrate comprising a circuit layer, the substrate including a first surface and a second surface opposite to the first surface, at least one recess recessed from the second surface and partially exposing the circuit layer, and a bottom surface of the circuit layer in the recess is recessed from the second surface of the substrate;
a first electronic component disposed above the first surface;
a second electronic component stacked adjacent to the first electronic component;
an encapsulation layer at least encapsulating the second electronic component and partially covering the second surface of the substrate; and
an electrical conductor extending from the second surface of the substrate into the recess of the substrate, and contacting the bottom surface of the circuit layer, wherein the substrate is projectively within a planar coverage of the first electronic component.

12. A semiconductor device package, comprising:
a substrate comprising a circuit layer, the substrate including a first surface and a second surface opposite to the first surface;
a first electronic component disposed above the first surface;
at least one second electronic component stacked adjacent to the first electronic component;
an encapsulation layer disposed in a cavity of the substrate and encapsulating the second electronic component, wherein the encapsulation layer includes a through hole exposing the circuit layer; and
an electrical conductor disposed in the through hole and in contact with the circuit layer, wherein a profile of the encapsulation layer at an elevation below the second surface of the substrate tapers toward the electrical conductor.

13. A semiconductor device package, comprising:
a substrate comprising a circuit layer, the substrate including a first surface and a second surface opposite to the first surface;
a first electronic component disposed above the first surface;
at least one second electronic component stacked adjacent to the first electronic component;
an encapsulation layer disposed in a cavity of the substrate and encapsulating the second electronic component, wherein the encapsulation layer includes a through hole exposing the circuit layer; and
an electrical conductor disposed in the through hole and in contact with the circuit layer, wherein the circuit layer comprises a bonding pad exposed from the second surface, and a surface of the bonding pad is substantially leveled with or recessed from the second surface.

14. The semiconductor device package of claim 13 , wherein a profile of the encapsulation layer at an elevation below the second surface of the substrate tapers away from the substrate.

15. The semiconductor device package of claim 13 , wherein the electrical conductor is in contact with an inner sidewall of the recess.

16. The semiconductor device package of claim 13 , wherein a surface of the encapsulation layer is substantially leveled with the second surface of the substrate.

17. A semiconductor device package, comprising:
a substrate comprising a circuit layer, the substrate including a first surface and a second surface opposite to the first surface;
a first electronic component disposed above the first surface;
at least one second electronic component stacked adjacent to the first electronic component;
an encapsulation layer disposed in a cavity of the substrate and encapsulating the second electronic component, wherein the encapsulation layer includes a through hole exposing the circuit layer; and
an electrical conductor disposed in the through hole and in contact with the circuit laye

Assignees

• Advanced Semiconductor Eng

Inventors

• Yen You-Lung
• Appelt Bernd Karl
• Essig Kay Stefan

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/121

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title