Parametrically activated quantum logic gates

US11677402B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11677402-B2
Application numberUS-202117410042-A
CountryUS
Kind codeB2
Filing dateAug 24, 2021
Priority dateJun 19, 2017
Publication dateJun 13, 2023
Grant dateJun 13, 2023

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.

First claim

Opening claim text (preview).

What is claimed is: 1. A quantum information control method comprising: generating a control signal configured to modulate, at a modulation frequency, a transition frequency of a tunable qubit device in a quantum processor, the modulation frequency being determined based on a transition frequency of a fixed-frequency qubit device in the quantum processor, the transition frequency of the fixed-frequency qubit device being independent of a magnetic flux experienced by the fixed-frequency qubit device; and applying a two-qubit quantum logic gate to a pair of qubits in the quantum processor by communicating the control signal to a control line coupled to the tunable qubit device, the pair of qubits comprising a first qubit defined by the fixed-frequency qubit device and a second qubit defined by the tunable qubit device, wherein applying the two-qubit quantum logic gate to the pair of qubits comprises one of the following: applying an iSWAP gate to the pair of qubits; applying a square-root-of-iSWAP gate to the pair of qubits; applying a controlled-Z gate to the pair of qubits; or applying a Bell-Rabi gate to the pair of qubits. 2. The method of claim 1 , comprising determining the modulation frequency based on the sum or the difference of: the transition frequency of the tunable qubit device, and the transition frequency of the fixed-frequency qubit device. 3. The method of claim 1 , wherein the modulation frequency is determined based on the transition frequency of the fixed-frequency qubit device and the transition frequency of the tunable qubit device. 4. The method of claim 1 , wherein the modulation frequency is determined based on the transition frequency of the fixed-frequency qubit device and the anharmonicity of the tunable qubit device. 5. The method of claim 1 , wherein the modulation frequency is determined based on the transition frequency between the ground state and first excited state of the fixed-frequency qubit device. 6. The method of claim 1 , wherein the modulation frequency is determined based on the transition frequency between the first excited state and second excited state of the fixed-frequency qubit device. 7. The method of claim 1 , wherein applying the two-qubit quantum logic gate to the pair of qubits comprises applying an iSWAP gate to the pair of qubits. 8. The method of claim 7 , wherein the control signal is configured to modulate the transition frequency of the tunable qubit device at the modulation frequency with a modulation amplitude ow, and the control signal is configured to produce an interaction between the tunable qubit device and the fixed-frequency qubit device for a total interaction time t i ⁢ S ⁢ W ⁢ A ⁢ P ( 1 ) = π 2 ⁢ 1 g | J 1 ⁡ ( δ ⁢ ω / ω m ) | , where g represents a capacitive coupling strength between the tunable qubit device and the fixed-frequency qubit device, J 1 represents a first-order Bessel function of the first kind, and ω m represents the modulation frequency. 9. The method of claim 1 , wherein applying the two-qubit quantum logic gate to the pair of qubits comprises applying a square-root-of-iSWAP gate to the pair of qubits. 10. The method of claim 9 , wherein the control signal is configured to modulate the transition frequency of the tunable qubit device at the modulation frequency with a modulation amplitude ow, and the control signal is configured to produce an interaction between the tunable qubit device and the fixed-frequency qubit device for a total interaction time t i ⁢ S ⁢ W ⁢ A ⁢ P ( 1 ) = π 4 ⁢ 1 g ⁢  J 1 ⁡ ( δ ⁢ ω / ω m , )  , where g represents a capacitive coupling strength between the tunable qubit device and the fixed-frequency qubit device, J 1 represents a first-order Bessel function of the first kind, and ω m represents the modulation frequency. 11. The method of claim 1 , comprising generating the control signal to modulate the transition frequency of the tunable qubit device about a reference frequency ω T 01 at the modulation frequency ω m =| ω T 01 −ω F 01 |, where ω F 01 represents the transition frequency of the fixed-frequency qubit device. 12. The method of claim 1 , wherein applying the two-qubit quantum logic gate to the pair of qubits comprises applying a controlled-Z gate to the pair of qubits. 13. The method of claim

Assignees

Inventors

Classifications

  • H03K19/195Primary

    using superconductive devices · CPC title

  • Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

  • Models of quantum computing, e.g. quantum circuits or universal quantum computers · CPC title

  • Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation · CPC title

  • Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title

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What does patent US11677402B2 cover?
In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by c…
Who is the assignee on this patent?
Rigetti & Co Llc
What technology area does this patent fall under?
Primary CPC classification H03K19/195. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 13 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).